Optimizing printed-circuit-board test coverage
Rick Nelson, Chief Editor -- Test & Measurement World, 8/1/2007 2:00:00 AM
Test engineers struggle to find the optimum balance between printed-circuit-board (PCB) cost and test coverage. Low coverage leads to excessive field returns, warranty replacements, and even lawsuits. Attempts to provide too much coverage lead to reduced profits, canceled projects, and even bankruptcy.
That’s the message Arden Bjerkeli, director of support, training, and services at Asset InterTech, delivers in the Webcast “Test Coverage Decisions for the Printed Circuit Assembly Factory.” Bjerkeli notes that several techniques are available to help diagnose and repair defects, prevent test escapes, and improve processes while minimizing costs:
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process monitoring and structural test, which use automated optical inspection (AOI), automated x-ray inspection (AXI), and manual visual inspection;
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electrical structural testing, including in-circuit test (ICT), flying probe test, and IEEE 1149.x JTAG; and
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functional board test, which can employ a system mock-up, self-diagnostics, simulation, emulation, or external instrumentation under control of a test executive.
Bjerkeli notes that these techniques can be combined, citing as an example a board having 128 pull-up resistors of the same value (figure). If all the resistors will be placed from the same reel, you can use ICT to check the value of only one and assume that the value of the other 127 is the same. Then, you can use AOI or AXI to verify that each resistor is present and aligned properly and that it exhibits high-quality solder joints. Finally, JTAG technology can ensure that each resistor is neither shorted nor open.
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You can combine ICT, inspection, and JTAG techniques to achieve a high level of coverage on 128 devices with only one test point on a signal net. |
He covers proposed standards for defining the structural PCB defect universe, including Agilent Technologies’ PCOLA/SOQ (for Presence, Correct, Orientation, Live, Alignment, Short, Open, Quality), ASTER Ingenierie’s PPVS (Presence, Polarity, Value, Solder), and Philips Research’s MPS (Material, Placement, Solder). He also covers iNEMI’s FAIM (Feature, At-speed, In-Parallel, Measurement) extension to PCOLA/SOQ as well as Philips Research’s DMPSF (Design, Material, Placement, Solder, Function).
For more details, view the archived Webcast, sponsored by Asset InterTech and Test & Measurement World, at www.tmworld.com/webcasts.
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ASTER Ingenierie is not the proper company name. It is ASTER Technologies.
DMPSF is not a Philips research but an ASTER Technologies models.
Christophe LOTZ - 2009-8-9 05:01:00 EDT
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