Simulator Test Tools Speed Circuit Design
An interactive version of Spice with built-in scope and schematic-probe functions eases design chores and lays the groundwork for test-program development.
Rick Nelson, Senior Technical Editor -- Test & Measurement World, 6/1/1999 2:00:00 AM
I came up with the kludge represented in Figures 1 through 3. A zero-crossing detector (Fig. 1) would convert an input sine wave (Vin) to a square wave, which when high would charge an op-amp integrator (Fig. 2). Subsequently, a reference-input square wave would discharge the integrator. The integrator output voltage at the conclusion of this charge/discharge cycle would represent the difference between the input- and reference-signal periods. This level could be captured by comparators and an output latch (Fig. 3).
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Figure 2. Analog switches SW1 and SW2 apply reference voltages to charge and discharge an integrator in response to input and reference signals, respectively. SW3 discharges the integrator after completion of a six-cycle measurement period. A level shifter conditions the output for driving the level detector in Figure 3. |
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Figure 3. A level detector digitizes the output voltage from Figure 2. A flip-flop samples the digitized output and captures it on a rising edge at the CLK input, which occurs at the end of each measurement cycle of the integrator of Figure 2. |
I made several enhancements to my basic design, because of problems I identified before putting cursor to screen and because of problems I encountered during circuit simulation as well as construction. First, I identified a shortcoming in the marketing spec—it failed to provide an update rate. I envisioned the output being a string of LEDs that would connect to the Figure 3 output latch. A once-per-half-cycle update at 440 Hz would obviously not be useful to the user.
Because the human ear does not detect sound-wave variations slower than about 12 to 20 Hz as pitch (they’re apprehended as beats), I reasoned that an update rate faster than about 20 Hz would be unnecessary. Consequently, I decided to drive the integrator for a period corresponding to several input and reference cycles. Eight cycles came to mind, as I had on hand a couple of 74HC164 8-bit serial-in, parallel-out shift registers. I initially reduced the cycle count to seven, reserving the shift registers’ eighth bit for resetting the integrator to zero after each measurement. This approach worked fine in the simulation, but the integrator did not seem to reliably reset within the allotted time at worst-case reference-to-input phase relationships in my breadboarded version, so I allocated an additional cycle for circuit reset.
I realized that reducing the number of cycles over which the integrator operated would place more stringent accuracy demands on the comparator-based level detectors in Figure 3. I was still pretty fuzzy on what a meaningful refresh rate would be anyway, and might find myself adding additional shift registers, so an initial choice of six cycles seemed as good as seven or eight. Further, I could see that the simulator would be of little help in this regard; I would ultimately have to put my marketing cap on and convene a focus group to evaluate the working prototype’s user interface. The ICAP/4 library doesn’t include focus-group models.
My eight-cycle approach—six for measurement and two for reset—would provide a refresh rate of 55 Hz at A440—higher than necessary, yet high enough to possibly extend the allowable reference frequency down at least one octave. I tabled further consideration of update rates pending focus-group results.
My Initiation as a Spice Boy
My next step was to capture the schematic from the notes and block diagrams I had jotted down. ICAP/4’s SpiceNet schematic-capture program, although it lacks features like rubber-banding that you’ll find in dedicated schematic programs, was easy to use, and I was able to populate my screen with components and wire them up quickly. My first effort at simulation was another matter altogether. I set up the reference voltage as 440 Hz and the input as 445 Hz and expected to see the results shown at the right-hand side of Figure 3: The Above_quartertone_high testpoint remaining low with the other three transitioning high at the end of the measurement period.
Instead, I was inundated with error messages, including “Node 15 can’t be analog and digital!” That message continues to stump me; it occurs whenever I connect a 74HCT14 Schmitt-trigger inverter to analog or other digital CMOS parts. I’ve referred this problem to the factory and meanwhile am using ’04 inverters instead of the Schmitt-trigger versions, although the latter seem perfectly happy to promiscuously connect to non-Schmitt-trigger parts in the real world.
I then began breadboarding the circuit, figuring I could defer simulation and its error messages until I had a working physical model. That approach, too, proved problematic. My input-signal circuitry through the zero-crossing detector worked fine, but my REF6 signal refused to stay high for six reference cycles.
Defeated on two fronts, I returned to the simulation and soon got the knack of making sure that diodes had part numbers assigned, that nodes weren’t left hanging, and that ICs had supply voltages properly connected. The simulation soon worked fine, as long as I avoided using Schmitt triggers.
At this point, I employed the two simulation modes that were most helpful in troubleshooting my prototype: AC and transient analysis. I used AC analysis to characterize the bandpass filter (Fig. 1). The simulator’s swept-parameter feature made it easy to determine the effect of various component values on filter response. Figure 4, for example, shows the frequency response for five values of C2.
I next initiated transient analysis. To set up the transient simulation in ICAP/4, I specified a time step size (for instance, 10 ms) and a total analysis time (about 20 ms to cover the eight-cycle—at 440 Hz—measurement and reset period). The simulation waveform vignettes in Figures 1 through 3 and the Intu-scope display in Figure 5 show simulation data from 3 to 23 ms; I suppressed display of data for the first 3 ms as nothing much of interest happens then.
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Figure 4. A simulator makes it easy to design filters. This Bode diagram, developed by the ICAP/4 swept-parameter capability and displayed using the Intuscope function, shows the effect of altering C2 (from 1 to 5 nF in 1-nF steps) in Figure 1 on the response of the bandpass filter. |
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Figure 5. Here, Intuscope displays key waveforms of the tuning-fork circuit. The top four digital waveforms represent the input signal, reference, six input cycles (IN6), and six reference cycles (REF6). The analog waveforms represent the integrator drive circuitry output Visrc (green), which delivers 5 V when the six-reference-cycle signal is high and –5 V when the six-input-cycle signal is high.
The output voltage Vout (red) increases when REF6 only is high, remains level when IN6 and REF6 are both high, and decreases when IN6 only is high. The back porch remaining after IN6 goes low represents the difference between input and reference frequencies. It is maintained for about 500 ms to facilitate latching by the output flip-flop (Fig. 3). |
The simulator’s transient analysis was helpful in characterizing the integrator and level-shifter’s performance, making it easy to ensure that the Vint signal remained within the 67.5-V limit mandated by the analog switch. Transient analysis was also helpful in fine-tuning a quick-and-dirty RC one-shot (which synchronizes the IN6 and REF6 signals to within one reference cycle) and two RC delays that provide adequate time for the output latch to acquire valid data.
These delays establish a “back porch” on the output voltage signal (beginning at 18.2 ms in Figure 5 and extending for about 500 ms) that allows adequate time for the output latch (Fig. 3) to acquire valid data. In other cases, though, the simulation’s slowness (about 3 min to simulate 20 ms of tuning-fork operation on a 233-MHz Pentium system) prompted me to experiment on the breadboard. For example, I developed a mental block about the shift-register reset circuitry in Figure 1 and found it much quicker to plug in real NAND and NOR gates to determine that a NOR gate was what was wanted. In fairness, I should note that had I entered my design in multiple subcircuits, I could have simulated subcircuits representing groups of components in isolation, speeding the simulation.
Having successfully simulated the circuit, I returned to the breadboard and the problem of the REF6 signal not remaining high for six reference cycles. At this point, I was deriving the reference voltage by using a PC’s line-out audio signal generated from a 440-Hz .WAV file to drive a comparator-based zero-crossing detector. Not having expected to need a 100-MHz scope to trouble-shoot this audio circuit, I at first didn’t notice the 200-ns glitches on the comparator outputs. The reference shift register did see these glitches, however (as I finally did after connecting a 100-MHz scope), and dutifully counted each one. Adding a differential input and bandpass filter between the PC and the reference zero-crossing detector solved this problem (Fig. 6). Although the simulator does not have a “noisy PC input” model, it does include various noise modeling features, but I am still attempting to duplicate in the simulator the real-world results I was seeing.
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Figure 6. The Vout signal in the breadboarded tuning-fork circuit mirrors Vout developed by the simulator in Figure 5, with a key exception. Figure 5 shows the ideal case, with all components having nominal value. The Vout waveform here (blue), shows a slight slope between the steeper charge and discharge regions. This slope stems from component mismatches in the Figure 2 circuitry driving the integrator and from op-amp bias currents. The REF6 signal shown here (red) remains high for six reference cycles; in my first breadboard, a noise problem caused it to reset prematurely. |
In one other area, the real world presented a problem that I didn’t see in the simulation. National Semiconductor’s data sheet for the CD4066B analog switch intimates that the part, when powered by a unipolar supply, will reliably switch 67.5-V analog voltages. The replacement-part NTE Electronics switches that I used, however, began conducting when either switch input/output terminal reached –1 V. This characteristic distorted the negative-going portion of the Visrc waveform and prevented the integrator from accurately developing negative voltages (which should appear when the input frequency is higher than the reference frequency). Adding a –5-V supply for the analog switches solved this problem.
With a working simulation and breadboard, it became time to investigate the effect of component tolerances on circuit performance. The back-porch voltage is critical. For a 440-Hz reference and 445-Hz input, the integrator back-porch level (at node 129) is nominally –542.71 mV. To investigate the effect of component tolerances on this value, I ran an RSS (root summed square) analysis that acquired the integrator output voltage at 18.4 ms.
RSS runs a circuit simulation for each component having a tolerance and measures that component’s effect on the measurement or measurements the simulator is set up to acquire. An RSS simulation is time consuming (about an hour for this circuit on a 233-MHz Pentium PC), but it’s hard work only for the computer, not for me. The results show that 2% resistors and 5% capacitors could cause the integrator back-porch voltage to range from –1.2954V to 210.02 mV—a wide range that would mandate time-consuming tweaking of the level detectors in Figure 3. (You can view the complete RSS report.)
The Cliffhanger
RSS analysis, however, presents worst-case results, and it’s valuable to ask what the chances are of obtaining these results in a production version of the circuit. In a random substitution of parts on my breadboard, I saw nowhere near the variation calculated by the RSS simulation. In a subsequent article, I will discuss Monte Carlo analysis and other simulation approaches to addressing this question. In addition, I will present a circuit fault tree and discuss the development of a final product acceptance test. And, of course, I will present my focus-group members’ comments on how pleased they are with product performance. T&MW
Copyright 1999, Test & Measurement World. Published by Cahners Business Information, Newton, MA.
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Read this article in a Some design-for-test tools from firms like LogicVision (San Jose, CA) require circuitry embedded with proprietary cores. I wanted to employ readily available standard components so I could easily build a prototype whose performance I could compare with the simulation results. Some test/simulation packages are tailored for specific production-test environments—for instance, Analogy’s mixed-signal Testify package emulates Teradyne (Boston, MA) and LTX (Westwood, MA) ATE systems. The Test Designer is sufficiently general to apply to various test environments, including benchtop trial-and-error. For my project—a tuning fork for the tone-deaf—I got to be my own marketing as well as design- and test-engineering departments. Negotiations between my marketing and engineering personalities (see my June staff column) yielded this design spec: The circuit would compare an input frequency with a 440-Hz reference; its full-scale range would be a quartertone above and below the reference frequency (427.5 to 452.9 Hz), and its accuracy should be within a 64th-tone (60.79 Hz). My goal was not to demonstrate any circuit-design virtuosity—I’ll save that for my colleagues at EDN, Test & Measurement World’s design-oriented sister publication. Instead, my goal was to solve the problem using parts that appear in the standard ICAP/4 Spice-model library and that I had on hand. Real EEs Don’t Use PLLs My first thoughts were to employ a phase-locked loop (PLL), but I rejected that approach for two reasons: I didn’t have a CD4046B chip, the only PLL in my ICAP/4 library, and more important, a one-chip solution wouldn’t be very interesting. I wanted an approach that would combine many linear and digital components and whose accuracy and repeatability would depend on potentially unstable and drifty analog voltage levels.
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The following is a letter that was published in the October 1, 1999 issue about this article: Spice—Is It Mixed Signal? Your article “Simulator Test Tools Speed Circuit Design” (June 1999, p. 34) is welcome coverage of simulation tools for PCB design and test analysis. However, your comment that “Spice is a mixed-signal simulator . . . ” is a bit misleading. Spice-based simulators are, in a way, mixed-signal, in that they can simulate digital as well as analog circuitry. But in most of these simulators, digital models are specified in terms of analog constructs and evaluated within the context of continuous time. Most digital effects are achieved using control-source-based macromodels, and solutions are achieved by evaluating analog algebraic and differential equations. Digital simulators, which were developed around event algorithms and digital abstractions to increase simulation speed, can evaluate digital models in terms of discrete states and in discrete time. To simulate the operation of digital devices, a mixed-signal simulator needs to have an event queue that can process discrete events (state changes at discrete time points). Of course, you could simulate digital devices with transistor-level models, but this is extremely costly in terms of processing time. Likewise, evaluating digital macromodels is inefficient because the simulator is still solving analog-type equations. True mixed-signal simulators have built in a solver for analog differential equations and an event queue to process state changes in discrete time. Similarly, Intusoft’s IsSpice4 has combined Georgia Tech’s XSpice event-driven algorithms with Berkeley’s Spice3 analog algorithms. Once the event queue requirement is met, the issue becomes one of accuracy and efficiency. To ensure that signal conversions are processed properly, the mixed-signal simulator must accurately process threshold crossings, as well as simple voltage/state measurements, that occur at analog/digital boundaries. And efficiency of simulation greatly depends on how the analog and digital simulation algorithms are synchronized, i.e., how and when information is passed between the analog algorithm and the event-driven algorithm. The synchronization method employed can affect simulation overall speed by up to 50x. The buyer of a mixed-signal simulator would be well advised to research how the event queue, threshold crossing, and synchronization are handled by the software. Also, I have one minor correction to your article. You stated that Analogy’s Testify test suite is tailored to Teradyne and LTX test environments. Testify, however, is a generic test suite that does not have ties to any test system or environment. Craig Siegel, Analogy, Beaverton, OR (Ed. Note:Look for a follow-up article about the Spice simulation in the October 15 issue of Test & Measurement World.) |
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