VHDL simulator flags inadequately tested code
-- Test & Measurement World, 11/2/2003 2:00:00 AM
The CoValidator VHDL simulator and coverage analyzer, the first component of Impulse's forthcoming CoDeveloper hardware/software design suite, enables users to quickly identify specific lines of code that are not adequately covered by their HDL test suites. It also identifies sections of the code that may be candidates for further testing, optimization, or elimination. Serving developers of VHDL applications for Xilinx, Altera, Actel, QuickLogic, and other FPGAs, CoValidator red-flags sections of source code that have not been executed, identifies branch conditions that have not been tested, and provides detailed coverage reports (in a variety of formats, including HTML) to help track the progress of test-suite development.
Color-coded graphs dynamically linked with the actual code (displayed in a context-sensitive source-code editing window) help engineers quickly visualize untested and unused segments of code. Coverage data may be generated from a single simulation run or from an entire test suite involving hundreds or thousands of test cases.
Price: $850 for a node-locked annual license; $1495 for a perpetual license. Impulse, Kirkland, WA. 425-576-4066;www.CoValidator.com.
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