Industry experts discuss the future of test at APEX’s Test and Inspection Summit
Gail Flower, Contributing Editor -- Test & Measurement World, 4/6/2009 1:12:00 PM
In Las Vegas, on April 1, 2009, during APEX, Rick Nelson, editor in chief of Test & Measurement World, moderated the Test and Inspection Summit.
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APEX highlights test and inspection suites and systems |
The industry panelists who discussed where test is headed this year included David Buhrkuhl, president SPEA America; Peter van den Eijnden, president JTAG Technologies; Mark Harding, director of sales, North America, Digitaltest; Jack Rozwat, general manager, SST Americas field operations, Agilent Technologies; Carsten Salewski, president and CEO, Viscom; and Phil Vere, managing director for bond test, Dage Precision Industries. An edited transcript follows.
Nelson: Last year, the Summit panelists talked about outsourcing test, especially to Asia. Some of the problems in test come about as new interconnect methods between die--such as through silicon vias (TSVs) and other methods enter into common practice. People aren’t going back to DIP-style packages, but they are going to new styles of SIP, POP, and other 3D stacked packaging types.
Last year, Steve Case of CyberOptics mentioned that process control for solder paste deposition can be assisted with many methods, such as AOI, electrical test, and X-ray. Choosing between which on is the bad news. Don Miller, president of YesTech, agreed that there is no one system that can handle all test issues.
The ever-growing increase in electronic complexity continues to challenge engineers who need to build testability into their products. As multi-die packages become more commonplace, the line between chip and board is blurring, and test processes face new challenges. Building on the 2008 Summit, this year’s panel discussed the latest test challenges and the emerging technologies to deal with them, including in-circuit electrical test, optical inspection, x-ray inspection, functional electrical test and JTAG/boundary-scan test.
Now, let’s meet this year’s panel.
Buhrkuhl: At APEX this year we are introducing a new flying probe, low-cost tester, knowing that cost control this year is more critical than ever. Programmed in-circuit saves time for new product introductions, and that’s one thing I suggest.
Van den Eijnden: Our 15-year-old company offers expertise in boundary-scan tests, which works well for flash devices, analog parts, or high-speed interconnects in small spaces.
Harding: Our 30-year-old company, located outside of Frankfurt, Germany, has many types of capabilities including in-circuit, functional, flying probe, AOI and X-ray.
Salewski: Our 25-year old company makes wafer inspection equipment for as x-ray and is headquartered in Hanover, Germany.
Rozwat: Agilent spinned out of HP and is now the largest supplier of test and measurement equipment. The 3070 is our latest in-circuit tester.
Vere: Dage does nondestructive test, such as x-ray, and bond testing.
Nelson: Do your offerings make the others obsolete?
Burkuhl: As the panel said last year, there’s no one system that solves all problems, even ours. But if you need a critical electronics product, let’s say a pacemaker, you probably want all types of tests, including vision, functional, and everything else available here from all panelists. If you’re buying a cell phone, you might not need such extensive testing. The flying probe that we supply is especially handy for big boards. Our product lets you determine if the right part is on the right board.
Van den Eijnden: We do high-volume testing. Process inspection is fairly easy. Structural test is of intermediate level. But as board space grows increasingly tighter, for testing with limited physical access to test points, you need to use boundary scan. For analog test, you need a whole spectrum of testers.
Harding: We provide flying probe and other board test systems. We partner with JTAG to integrate boundary scan. I’m surprised to see so much in-circuit test. Customers just won’t pay for fixturing any longer. But we keep supporting fixtures already developed on our machines. We don’t offer AOI or x-ray, but those are useful too.
Rozwat: People are reducing budget amounts set aside for test. In electrical test, built-in testability, such as boundary scan, is necessary. And we should take advantage of any type of validation test that can be built into silicon.
Salewski: We already know that there’s not one single solution. In fact, the real question is: What is the cost of failure? Many types of test are needed to check functionality, quality, and so forth. Does the test strategy make sense? Approximately 90% of all testing in electronics is done using AOI inspection of solder joints.
The more you know about the process of electronics manufacturing, the better you can know what types of test fit. To do it right, rather than doing it again is the goal. DFT (design for test) moves the process during the beginning. That’s where we start.
Vere: I agree. Designing a product to be tested should be an integral part of NPI (new product introduction). Virtual simulation models aren’t enough though. You need to have test strategies ready for products early on.
Nelson: Is X-ray too expensive?
Rozwat: Yes. It’s not perfect.
Salewski: Again, what’s the cost of failure? Viscom has aggressive pricing. AOI and x-ray are both expensive, but there’s no other way to see under BGAs for hidden joint inspection.
Vere: X-ray inspection isn’t expensive enough. We offer down to 100-nm resolution, and getting down to these fine levels requires costly R&D.
Buhrkuhl: We cannot test all BGAs using just electrical test, however BGAs can be tested using boundary scan. X-ray can help find counterfeit components or the absence of wire bonds. We cannot do away with functional tests, of course. Additionally, there may be 1536 pins in a device today, but the price of testing has gone down. Anything to speed up testing or to check design layouts in the beginning provides quality information.
Audience question: How do you reduce the cost of test?
Van den Eijnden: With boundary scan, you don’t need as much in-circuit test. Boundary scan drives the pin, and it’s built into chips already. And boundary scan equipment is far less expensive than in-circuit test. In-circuit testers are by nature expensive, as is fixturing. I must admit though, that newer in-circuit testers can be less expensive than older models.
Harding: In-circuit test won’t go away, though many say that it is fading. In a high-mix, low-volume environment, in-circuit remains a useful test.
Rozwat: We have seen a 50% drop in test over the last two years. Agilent now offers boundary scan.
Salewski: There is a gap between different types of test.
Vere: You have to make equipment scalable. And engineers need to be involved in the DFT early stage. We need to build that culture of understanding at all levels.
Van den Eijnden: You’re right. Design engineers out of school haven’t a clue as to what’s happening on the production floor. DFM and DFT test may have conflicts. All expertise isn’t developed in school, and for that multidisciplinary teams are important.
Buhrkuhl: Most companies understand the need for DFT, and most have it now. A design engineer should probably spend a week as a trouble shooter on the floor to advance his/her knowledge.
Rozwat: Right. Each engineer needs to have experience in many process areas.
Audience question: What about design constraints?
Rozwat: Access and design constraints are problematic. The newer probes are designed to fit into tight spaces.
Van den Eijnden: Once again, access is built into the silicon for boundary scan. The 1149.1 is the first IEEE standard for testing the connection between pins.
Now 50 PLD devices can be programmed simultaneously. We need to harmonize the many accessible logic solutions.
Salewski: That’s where AOI and x-ray come into test to answer in areas where complexity offers less access.
Nelson: How does the evolving JTAG standard address what you’re doing in test?
Buhrkuhl: Boundary scan and flying probe tests can be combined.
Rozwat: Boundary scan combined with Test Jet technology can eliminate extra tests. Boundary scan is coming of age now.
Nelson: What about testing the new stacked devices? They’re somewhat like PCBs with interconnect between wafers. When and where will they undergo test?
Salewski: AOI will be used. Strategies to establish what is good and what is bad will need to be established.
Van den Eijnden: There are tools available now. SIP is like any other part. The use of software and automation will become more important for collecting, finding, compressing and interpreting data.
Buhrkuhl: Flying probe test software has improved over the last two years using vectorless testing.
Audience question: How can you build more functionality into packages, including test?
Rozwat: With boundary scan.
Summit transcript prepared and edited by Gail Flower, Contributing Editor.
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