Test's role on the path to zero-defect devices
By Mick Tegethoff and Vivek Chickermani, Cadence Design Systems -- Test & Measurement World, 6/1/2006 2:00:00 AM
| Read more about meeting the individual challenges of digital zero-defect testing and details of approaches to dealing with these challenges. |
The effectiveness of semiconductor manufacturing test has a direct impact on the quality of shipped silicon and on the economical efficiency of the overall test cost in the supply chain. Typically, suppliers and customers have negotiated agreements on acceptable defects per million (DPM) levels that represent an optimum tradeoff between test coverage and cost. Applications in the medical, automotive, and aerospace fields, however, have quality requirements that supersede supply-chain optimization considerations. In these environments, achieving "zero defects" is the objective and the main challenge.
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| The zero-defect manufacturing test ecosystem extends from design and verification through wafer sort and manufacturing test and on to diagnostics. |
In many applications requiring zero defects, engineers traditionally focused on testing analog circuits and on addressing overall reliability. Vendors and customers did not have to devote expensive resources to testing digital components, because the digital content was small, and digital devices were predictable in terms of their defect behavior.
Today, however, the digital content of zero-defect applications is increasing significantly, and designs are migrating to 90-, 65-, and even 45-nm technology nodes. At these advanced nodes, defect behavior of digital circuitry is far less predictable using traditional fault models. Today's designs continue to require the traditional structural-test techniques, but they also require specialized fault modeling and test procedures to detect the subtle timing defects that can appear in nanometer designs.
Successful zero-defect designs require a full-chip test infrastructure; the ability to perform stuck-at, at-speed, and faster-than-at-speed tests; and tests that target defect-based fault models, all in an architecture that supports test cost management by using on-chip compression. In addition, process improvement requires volume diagnostics that can identify yield limiters as well as precision diagnostics to locate root failures. To read more about meeting the individual challenges of digital zero-defect testing and to learn details of approaches to dealing with these challenges, click here.
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