Post-test inspection boosts die yields
IC manufacturers rely on optical inspections at the end of fab lines to catch physical imperfections as well as defects caused by final-test probers.
By Jon Titus, Contributing Technical Editor -- Test & Measurement World, 6/1/2006 2:00:00 AM
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READ OTHER JUNE ARTICLES: Contents, June 2006 SIDEBARS: What's a hoop ring? Pre-test inspect, too |
Wafers produced for products as diverse as LEDs and MP3 players vary greatly in function, but they have one thing in common: They often undergo optical inspection after they pass an electrical test.
Increasingly, wafer fabs are turning to automated optical inspection (AOI) equipment to locate defects so they can deliver known-good die and simultaneously increase their yields. Unlike human inspectors, AOI equipment consistently locates and classifies defects, and it provides information that process engineers can use to track and head off potential problems.
But why would wafers of flash-memories, LEDs, or other devices require a final visual examination? After all, they just went through an electrical test that identified faulty devices. The answer is that an electrical tester cannot identify defects such as scratches, nicks, and missing passivation material that might lead to problems later in a product's life.
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Figure 1. (Top) These octagonal bond pads show the small marks made by test probes. (Bottom) A close-up view shows scrape marks and the relative size of probe marks on small pads. Courtesy of Rudolph Technologies. |
Another reason is that the electrical tester itself can be the source of problems, because the movement of test probes as they touch a wafer can create defects. Individual probes should touch only a bonding pad and leave only a small mark (Figure 1). Smaller semiconductor geometries, however, decrease the area of bonding pads, which makes them more difficult targets for a prober to "hit."
During electrical testing, slight misalignments may cause probes to damage passivation material that surrounds a pad and thus open semiconductor areas to destructive moisture (Figure 2). If a probe hits a pad at too great an angle, it might scrape off metal that can cause a short circuit in a packaged device.
Even when a probe touches down in the center of a pad, the physical contact can gouge or scrape the pad, which leads to a poor bond between the pad and a connecting wire. Although enough of a wire-to-pad bond can exist to let a packaged device pass final electrical tests, later on a small stress may cause the wire bond to fail.
"In a stacked-die package, those bond pads attach to other devices," said Mike Plisinski, VP and GM of the data-analysis and review business unit at Rudolph Technologies. "So, if you have combined five expensive die and one of them has a bond-pad defect you didn't find, you have 'killed' the four good devices and wasted an expensive package."
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| Figure 2. This image shows a probe mark that exceeded the limits of a bond pad and damaged surrounding passivation material. Courtesy of Camtek. |
To guard against such defects, probe-mark inspection (PMI) has become a key back-end step on wafer-fab lines. Most back-end wafer-inspection systems determine if a probe mark is too big or if a probe has run off a pad or has broken through the passivation material. Inspection results let process engineers find physical defects that could have harmed a die, even though the die passed electrical tests. The AOI equipment that examines probe marks also detects and measures the dimensions of foreign materials, scratches, polyimide delamination, photo-resist residue, and nicks on wafer edges (Figure 3).
In addition to detecting probe-mark defects, inspection equipment can measure the distance between a probe mark and a pad's edge. "You reject a die if a probe touched the passivation window," said Amir Gilead, VP of the semiconductor-inspection products division at Camtek, "but on some wafers, you reject a die if probe marks get too close to the passivation material. You don't want to take a chance that greater probe excursions will hit the passivation material." Process engineers preset the probe-to-passivation thresholds based on the wafer types they will inspect.
To properly inspect a wafer, inspection equipment must "learn" what a good die looks like and how to find the bond pads. That process varies from vendor to vendor.
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| Figure 3. Post-test inspection software can detect and classify defects such as (top) foreign materials and (bottom) a scratch. Courtesy of ICOS Vision Systems. |
Although CAD files might simplify the training of an AOI system to locate die features, process engineers often don't have that type of information, according to Rudolph Technologies' Plisinski. "Even if they had those files, they still would have to manually align the wafer with the inspection system because lithography patterns may have shifted slightly on a wafer's surface during fabrication. So, engineers start with a wafer on a chuck in Rudolph's NSX August inspection system and go through a series of automated setup steps that take only a few minutes and depend on the required 'recipe' options."
The engineers then program the system with bond-pad characteristics. As it runs a geometrical pattern match during a wafer scan, the system automatically finds the pads. "The pad-location process takes only a few minutes," said Plisinski. "Some engineers label each pad so they can easily track changes in probe-mark characteristics or positions."
ICOS Vision Systems uses a recipe for each wafer type to set up its WI-2000 inspection station. Gert Sablon, product manager for wafer inspection products at ICOS, explained that process engineers start with an example wafer on which they locate a perfect or close-to-perfect die. An image of that die provides the reference for comparisons and becomes part of the recipe. The recipe also contains reference information about other types of defects, such as nicks, scratches, and so on. Software compares scanned wafer images with the reference image and groups visual features into defect categories that process engineers have established.
Carl Smets, research and development director at ICOS, stressed the importance of proper alignment in an inspection system. "If you have diced wafers or diced wafers on hoop rings, slight stretching may change the position and orientation of the die from what you would find on an undiced wafer. So, to inspect the wafer properly, you must perform an accurate alignment for individual die." (See "What's a hoop ring?") ICOS employs scalable DSP processors in its inspection system to align die positions with recipe information that includes a reference-die image.
The Falcon 500 from Camtek requires about 15 min to set up. Instead of relying on a known-good die, the system uses a proprietary technique that scans die on a production wafer to create a "clean-reference" image for comparison.
"A user or process engineer doesn't have to know in advance which wafers or die are good," explained Camtek's Gilead. "They can even take bad die with defects and still generate a good reference. A minimum of five die will provide a clean-reference image, although engineers report using an average of seven to nine die. They can increase the number of die scanned when they observe wide color variations across a wafer." Process engineers can schedule "relearn," or update, scans that let the system adjust to process variations. (Camtek has several patents pending on its inspection technologies.)
After the learning step, operators can set run-time parameters such as the sizes of defects and the acceptable sizes of probe marks. "Some engineers may want to find defects above 25 microns," said Gilead. "So, they set the system to ignore anything 25 microns or smaller. They have complete control of inspection criteria."
Classify defects
After an inspection system acquires die images, automatic defect-classification software sorts defects into categories such as scratch, pit, or probe mark. The recipe for a given wafer type includes defect classifications and parameters.
"The classifications depend on what users require," explained Smets of ICOS. "You can classify a scratch as a long object with a length greater than x and a width greater than y. But pits, for example, are typically round, so they have only a diameter dimension. Process engineers combine characteristics such as position, dimensions, and optical contrast with logical operations such as AND, OR, and IF to classify defects."
The economic benefits of post-test inspection center on how many die a system can inspect in a given time and how many "false calls" its software produces. (A false call identifies a defect where none exists.)
"Engineers see a wafer move quickly on a chuck and think speed is everything," said Gilead of Camtek. A company's profits depend to a great extent on how many wafers it can inspect in a day, not just to how fast it can scan each wafer, so productivity calculations must include setup times as well as scanning speeds. "Say it takes two hours to set up System A and 15 minutes to set up System B," said Gilead. "If you inspect three types of wafers in a day, you spend six hours versus 45 minutes on setup. Even if System A scans faster than System B, the latter may offer a higher efficiency."
Engineers also should pay attention to the balance between scanning speed and the size of the defects they want to detect. Equipment may offer a scanning speed of x wafers/hr and a capability to detect defects as small as, say, 2 micrometers. But an inspection system cannot provide both capabilities simultaneously, cautioned Gilead. "If you need a higher resolution, or a higher magnification, to find smaller and smaller defects, the inspection speed decreases in proportion."
At the end of an inspection run, software identifies defective die so process engineers or operators can "reverify" the defects found. People review the defects and classify them as critical or noncritical. This process requires extra time and money, and cuts productivity, but you may need to do it.
Suppose your AOI system reports 20 defective die, but unknown to you, only three have critical defects. Can you afford to throw away all 20? Probably not. So you inspect all 20 and scrap only the three bad ones. The reverification step not only reclaims good die, but also lets you tighten your inspection criteria so subsequent inspections identify fewer false-call defects. But you must balance the benefits of eliminating false calls against the possibility that tighter specs will let AOI software pass defective die.
Economic benefits accrue from another aspect of post-test inspection—statistical process-control (SPC) information derived from inspection results. Using this quantitative information, equipment operators can identify and correct immediate problems. In addition, process engineers can examine long-term trends to determine, for example, why a probe pin has gone out of alignment or shows an excursion toward the edge of a bond pad.
"Say probe marks start to drift to the left and cause defects," said Plisinski of Rudolph Technologies. "The engineers see this trend, determine which prober causes the problem, and correct it. Or they may use the SPC data to uncover a problem with their alignment recipe."
The inspection information also lets engineers "stack" images to look for wafer-to-wafer trends. If they see scratches in the same place on many wafers, the SPC information can lead them to a robot end effector as the problem, explained Plisinski.
Until now, you may have thought a final electrical test provided the last word about the quality of your die. Placing an inspection system after the last test station, though, will help you weed out defective die you didn't know existed, keep test processes in control, and reduce field failures.
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