ITC 2008: JTAG Technologies, Teseda tout Teradyne initiatives
-- Test & Measurement World, 11/3/2008 11:38:00 AM
Representatives of JTAG Technologies and Teseda were on hand at the International Test Conference to describe separate initiatives in conjunction with Teradyne—involving TestStation boundary-scan integration and silicon debug, respectively.
First, Teradyne and JTAG Technologies have jointly demonstrated the ability to test and diagnose advanced digital networks with an integrated boundary-scan tool running on the Teradyne TestStation, enabling TestStation users to expand the test coverage achieved via boundary-scan on their boards to include LVDS devices, AC-coupled devices, and others.
Teradyne’s TestStation digital network board test system is based upon the JTAG ProVision environment using features of the IEEE 1149.6 standard, an enhancement of the 1149.1 specification. In addition to supporting 1149.1 tests, ProVision automatically detects the presence of 1149.6-testable networks, creating test patterns that detect and diagnose a wide variety of structural faults such as shorted coupling capacitors and faults on individual legs of a differential pair. Within ProVision, the tests can be verified on the workbench using a JTAG Technologies boundary-scan controller, prior to fixture development.
Following test verification and fixture development, the test applications, including the dot 6 patterns, are compiled and formatted for the Teradyne Run Time System (RTS) and Deep Serial Memory (DSM) card. Teradyne’s RTS, acting as the boundary-scan controller, applies the test bit-streams to the JTAG Test Access Port (TAP) using the DSM and captures the test data. Test results are then interpreted by the JTAG Technologies Boundary-Scan Diagnostic (BSD) module, which reports back automatically to the operator with easy-to-understand pin-level diagnostic messages.
Teradyne and Teseda team up on time-to-market and yield enhancement
Teradyne is also collaborating with Teseda on an integration of the IG-XL programming environment with Teseda’s Diagnostic Manager Series toolset and WorkBench (TWB) software to help customers achieve an expanded capability to perform silicon debug, failure analysis, and yield learning on Teradyne test platforms with a resulting decrease in time-to-market and improvement in profitability.
The Teseda toolset will utilize real-time results from the tester, along with design hierarchy, scan-chain structures, and diagnostic information generated by DFT tools from major EDA vendors to diagnose scan failures down to the gate and cell level. The goal of this new partnership is to allow Teradyne customers to perform these functions directly on an UltraFLEX or J750 platform in either a laboratory or production setting, using the same applications hardware and test program that will be deployed for volume production. The testers will collect results from volume production runs that will be used by Teseda’s toolset to identify areas of the circuit design that are sensitive to fabrication errors at smaller device geometries in order to improve overall yield.
www.jtag.com
www.teradyne.com
www.teseda.com
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