LSI Logic employs statistical processing to overcome deep submicron SOC quality barriers
-- Test & Measurement World, 4/16/2003 2:00:00 AM
LSI Logic (www.lsilogic.com) has announced the release of its Statistical Post-Processing test methodology for defect screening on deep-submicron system-on-chip (SOC) designs. Developed in collaboration with Portland State University, LSI Logic has applied the methodology to its ASIC production environment for 0.18-micrometer (G12) and 0.11-micrometer (Gflx) process technologies. Demonstrating a 30% to 60% decrease in failure rate measured by defects-per-million (DPM) units and early-failure-rate (EFR) values, this defect-screening approach is especially suited to applications often found in the communications and storage markets, according to Lucas Tsai, senior marketing manager of the company's Advanced Silicon Products division.
Tsai points out that the move to 300-mm wafers, the use of copper interconnects, and the emergence of deep-submicron integration are all making it difficult for chip vendors to maintain the quality levels they achieved with older process technologies. The reduced VDD levels and inherently high IDDQ levels of deep-submicron devices are increasingly straining traditional test techniques. The challenges posed by advances in technology are compounded, he says, by the fact that it is not uncommon for a chip to travel in the design and manufacturing phases through multiple locations for IP integration, physical implementation, wafer fabrication, wafer sort, packaging, final test, and burn-in. Handling multiple data sources and managing test data flow becomes a critical factor in maintaining quality levels.
To improve quality levels, LSI Logic's Statistical Post-Processing testing methodology identifies unusual data values or statistical "outliers" by using raw data from ATE and wafer-sort maps. Post-processing modules for major defect categories estimate and factor out the defect-free contributions so the defects can be clearly identified and screened. This level of defect screening efficiency cannot be achieved with traditional on-tester methods or burn-in. User-definable adaptive test thresholds maximize quality and throughput.
According to Bob Madge, director of advanced product engineering at LSI Logic. "Our Statistical Post-Processing methods combined with high fault coverage have resulted in 99.9% defect coverage for all defect categories."
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