ITC: Synopsys debuts small-delay-defect, power-management, and yield tools
-- Test & Measurement World, 10/29/2007 11:15:00 AM
Synopsys at the International Test Conference announced availability of its TetraMAX small-delay-defect automatic test pattern generator (ATPG), extended low-power-management capabilities within the Synopsys Galaxy environment, and a new Odyssey DFT yield-management module.
Synopsys reports that customers have validated the new TetraMAX small-delay-defect test capability on manufactured designs, identifying problems in some devices that had previously passed standard at-speed tests. Small delay defect ATPG creates patterns to test the smallest defects inside integrated circuits (ICs) that could lead to failures when the devices are operated at full speed.
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"Our member companies value innovations that improve the quality of manufacturing tests, and we believe Synopsys' TetraMAX small delay defect ATPG is an excellent achievement," said Yoshio Okamura, VP and GM of Development Department-2 at the Semiconductor Technology Academic Research Center (STARC), a research and development consortium founded by major Japanese semiconductor companies. "Synopsys' new test technology will identify failures caused by small delay defects that were not detectable before. Small delay defect testing has important ramifications for our member companies, and to all semiconductor firms dedicated to continually improving product quality."
To detect the small delay defects that can result from process variations, Synopsys enhanced its pattern generation capability to utilize precise timing information to target very small timing slacks. Designers can pass a circuit's detailed parasitic information from Synopsys' Star-RCXT extraction tool to Synopsys' PrimeTime static timing analysis tool, then use pin-slack information generated from the timing analysis to create small delay defect patterns using the TetraMAX ATPG technology. The new ATPG technique is consistent with existing design-for-test (DFT) methodologies and does not require changes to a design.
"Synopsys' collaboration with a majority of the world's top semiconductor firms has proven that TetraMAX small delay defect ATPG is capable of identifying subtle timing defects that escape traditional at-speed testing," said Gal Hasson, senior director of synthesis and test marketing at Synopsys. "We regard this successful validation of our timing-aware pattern generation capability as a critical milestone, and anticipate the new TetraMAX feature will lead to lower test escapes and ultimately lower test costs for our customers."
Low power management
Synopsys targets the new low power management capabilities in the Synopsys Galaxy test platform at reducing the time and effort needed to generate high-quality, power-aware manufacturing tests for integrated circuits (ICs). The TetraMAX ATPG tool now creates tests reflecting designers' power budgets, and the DFT MAX scan compression product further automates integration of design-for-test (DFT) structures in designs that deploy advanced low power management techniques.
New functionality in the TetraMAX product limits power consumption during scan test by automatically reducing switching activity to levels consistent with normal operation, based on designer-specified power budgets. This is achieved without compromising the cost-savings advantage of DFT MAX scan compression and test coverage.
Automation to manage power consumption also facilitates testing of subtle delay defects in nanometer devices. "Synopsys' TetraMAX small delay defect pattern generation capability detects timing problems associated with paths having very small timing margins," stated Dr. Tom Williams, a Synopsys fellow. "Because excessive power consumption can affect the delays of such paths, automation to manage it is now included in TetraMAX as part of Synopsys' comprehensive ATPG solution for achieving ultra-high test quality."
Besides adding capabilities to limit power consumption during test, Synopsys has enhanced DFT MAX to simplify the implementation of DFT in designs with multiple voltage domains. DFT MAX power optimization minimizes the number of scan chain connections that cross voltage domains, lowering the area impact of DFT by reducing the number of required level shifters and power isolation cells. Power intent affecting both scan domains and power domains, and specified in the Accellera standard Unified Power Format (UPF), is now preserved throughout the Galaxy platform flow, from synthesis through physical implementation and sign-off.
"Designers benefit from the ability to quickly and easily generate high-quality, low-cost manufacturing tests while preserving their power intent," said Antun Domic, senior VP and GM of the Synopsys implementation group. "Automation of low-power management in the Galaxy platform is consistent with Synopsys' commitment to provide our customers a comprehensive design platform that makes possible concurrent optimization of timing, signal integrity, area, power, and test."
Odyssey DFT yield module
Synopsys also announced that its Odyssey yield management software has been adopted by various semiconductor manufacturers to correlate and analyze diverse datasets needed for product yield enhancement. TetraMAX creates manufacturing test patterns and identifies logic in a design that could contribute to observed tester failures. TetraMAX failure diagnostics data is exported to the new Odyssey DFT module to facilitate comprehensive failure analysis and rapid yield improvement of fabricated devices.
"If a device fails production test, we want to understand why," said Bruce Cory, DFT manager at NVIDIA. "The Synopsys yield-management solution allows us to leverage design, fabrication, and production test data to analyze TetraMAX diagnostic isolations across multiple die and wafers. The software helps identify underlying failure signatures to enable faster yield ramp."
Semiconductor foundries typically supply their fabless clientele with parametric data associated with the manufacture and testing of production parts, but until now there was little designers could do with the information to improve product yield. With the Synopsys tools in-hand, designers are now leveraging the foundry-supplied data together with failure diagnostics accumulated from production runs (a capability often referred to as "volume diagnostics") to help determine the root cause of yield loss.
For example, designers at NVIDIA and TranSwitch are using the Odyssey module to correlate circuit failure candidates reported by TetraMAX diagnostics with foundry-supplied information. Data mining and cross-correlation features in Odyssey assist designers in quickly determining both the impact of measured process parameters on product yield and whether failing parts are caused by systematic or random processes.
"Nanometer manufacturing steps can distort device and wire geometries, leading to more frequent failures at process corners," said Zahi Abuhamdeh, director of DFT and diagnostics at TranSwitch. "Also, the foundry's occasional tweaking of the process can cause subtle corner failures that previously did not occur. The Synopsys yield enhancement solution has provided us the ability to determine whether failing parts from a product run are due to foundry, specification, or design-specific issues. In the latter scenario, making alterations to a single library cell or including or removing a foundry-recommended design rule might lead to a step-increase in the product's yield."
"Synopsys is committed to providing both foundries and their fabless clientele the latest innovations in ATPG diagnostics and yield management systems," said Dr. J. Tracy Weed, director of the manufacturing products group at Synopsys. "With the Odyssey DFT module, our customers now have vastly improved automation that enables analysis of product-specific diagnostics, design and foundry-supplied data to identify yield delimiters that present a barrier to higher profitability."
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