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Test & Measurement World Webcasts

-- Test & Measurement World, 11/18/2004 10:24:00 AM

Featuring engineering experts from test, measurement, and vision companies, these Webcasts provide tips for solving test problems. Each Webcast lasts approximately 1 hour and includes a question-and-answer session.

Upcoming Webcasts:

March 2008

Develop Better Test Systems with Advanced Data Management

Date: Wednesday, March 19, 2008
Time: 11:00 AM PDT / 2:00 PM EDT

Learn how the best practitioners in communications and electronics rely on proven, cost–effective, off-the-shelf test data management solutions to accelerate and simplify test system development, while increasing control of their remote test activities.

In this webcast you will learn:

The nature of test data, and the impact it can have at different stages of the product lifecycle
How centralized test data facilitates data mining and analysis, making it easier to react to production results
To what extent different departments within an organization can leverage test data to improve product quality
How to build a business case that justifies investment in an off-the-shelf data management solution

With practical examples of the Proligent™ solution, we will demonstrate how to:

Capture and manage test data in a central database
Automatically deploy engineering changes to test systems in the field
Manage product versions efficiently
Gain real-time visibility over production with web-based reporting

Overview of the Latest Test Methodologies for High Speed Serial Designs

Date: Monday, March 17, 2008 Time: 11:00am PT / 2:00pm ET Increasing data rates on the next generation Serial Data standards are creating new measurement challenges for all layers of the protocol stack. Tektronix understands these challenges and has a variety of tools available to address even the most complex of test requirements. This toolset includes solutions for signal integrity and compliance testing, receiver testing, digital validation and debug, and serial data link and network analysis. In this webinar we will touch on the most common as well the as the most challenging measurement tasks and how Tektronix solutions can help to better characterize and validate your high speed design.

Register for this webcast now

January 2008

Embedded Design Techniques for Optimizing Control Parameters

Date: Wednesday January 23, 2008
Time: 12 PM ET, 9 AM PT

In the process of optimizing control functions, small adjustments in microcontroller firmware can produce significant improvements in embedded system performance.
Coming up with the right values for gains, offsets, delays, hysteresis values and PWM parameters can be time consuming, but using the right tools can speed the process.
While it’s possible to optimize control systems through calculation and modeling, there are newer methods to speed and simplify the process.

This webcast on Embedded Design Techniques for Optimizing Control Parameters shows how today’s design tools enable faster real-world measurements and simpler determination of optimal design settings. We will discuss how flash memory, flexible development environments, and the capabilities of modern deep-memory, mixed signal oscilloscopes help monitor many points simultaneously, and combine to form a powerful solution toolkit.

You will learn in the webcast:

The use of specific measurement techniques to optimize key control parameters in your microcontroller-based systems
How to quickly determine the best operating points for a complex system design
How you can quickly and easily determine appropriate values for common settings such as gain, offset, and delay to deliver significant improvements in the performance of your embedded system

December 2007

Six hints for better scope probing

Date Aired: Wednesday, December 12, 2007, available on Demand until December 11, 2008
Time: 2:00 pm ET/11:00 am PT

Proper probing is critical to making quality oscilloscope measurements. Selecting the correct probe for your application and using the probe correctly means the difference between accurate representation of your signal and distorted or misleading results. In this web seminar, you will learn six useful hints for making better oscilloscope measurements. After attending you will be able to avoid most common probing pitfalls.

Register now for the webcast Six Hints for Bettery Scope Probing
November 2007

Advanced Radar Measurements

Date: Wednesday November 28, 2007
Time: 12 PM ET, 9 AM PT

Modern Radar must gather more information and make decisions faster than ever before. This can be accomplished by transmitting modulated pulses. Advanced Radars often use chirp modulation and ever increasing bandwidth to increase the range resolution, as well as to determine more information about the target, or even multiple targets. These pulses present difficult measurement challenges, as even small phase errors can introduce false targets.

The seminar on "Advanced Radar Measurements" will discuss some of the latest measurements for chirped Radar, Hopped Radar and very wideband Radars. We will discuss the measurement problems that need to be solved, and the solutions for these problems. Measurement results will be shown for pulses with 10 to 100 MHz width, as well as extremely wideband chirps 2 GHz wide.

You will learn in this webcast:

Measurements which are important to characterize the linearity of chirped pulses.
Measurements to characterize frequency-hopped pulses.
Techniques for discovering interference to, or time varying defects within, pulses.

December 2007

Maximizing the Impact of Test Engineering

Date: Wednesday, December 5, 2007 Time: 12:00 PM PST With product launch cycles accelerating, and with electronics complexity increasing every year, test engineering is now more critical than ever to new product success. Test systems have to be developed and deployed quickly—locally and at EMS sites worldwide—so that product launches are on time and the company remains competitive. Design and test engineers facing these pressures will learn about Enterprise Test Software (ETS), an innovation designed to integrate and synchronize test systems to other enterprise functions such as R&D, NPI, and manufacturing. By initiating test engineering early in the cycle—and feeding production information back into design—products will reach maturity faster, giving engineers a greater impact on their success. In this webcast, you will learn how to: Accelerate test system development Maximize engineering collaboration Streamline new product introduction Control and deploy test plans automatically Eliminate error-prone information exchange Standardize on best practices from day one

Pass PCI Express Physical Layer Compliance Testing the First Time

Date: Tuesday, December 11, 2007
Time: 1pm EST / 10am PST

With the PCIe 2.0 specification, 5.0 GT/s as well as 2.5 GT/s receiver testing are emerging as a key requirement for chip designers and add-in card vendors. In this seminar we look at why the requirements have been set the way they have, and some of the practicalities of making the measurement. We will then look at key transmitter measurements such as PLL characterization, jitter measurement in the presence of de-emphasis, de-emphasis ratio and dual port measurements. Measured examples of real devices will be used to illustrate the requirements.

What you will learn:

Why some key aspects of the standard are the way they are, including system architecture and the importance of clock distribution.
Understand the important aspects of transmitter, clock PLL and receiver testing.
See practical example measurements of each.

Recent Webcasts:

October 2007

How to Solve DDR Signal Integrity Validation Challenges

Date: Thursday, October 18, 2007 Time: 11:00 AM PDT/2:00 PM EDT Today, memory devices are found almost everywhere from computers and automobiles to test equipment and consumer products. One of the most commonly used memory technology designs is DDR SDRAM (double data rate synchronous dynamic random access memory). The DDR memory technology is evolving, creating faster transfer rate and lower energy consumption memory. DDR memory technology which is essentially parallel bus technology is reaching the speeds of serial technology. As the speed increases, the validation effort increases exponentially. In order for the memory system to function accurately, its signal integrity performance must meet certain minimum requirements. Signal integrity is the key to the system interoperability, or the guarantee that the devices from different vendors will integrate well when they are used together. This presentation outlines the challenges as well as the probing methods and tools for DDR signal validation. These methods are applicable for DDR, DDR2, DDR3 and SDRAM side of Fully Buffered DIMM system debug. Register now for this free webcast on DDR SDRAM

Webcast Date: October 10, 2007 1PM EDT

Make the most out of your automated test system from lab to enterprise. This tutorial will show you how to accelerate and optimize the design, characterization, verification, and validation of your products by applying the latest automated test and information management technologies.

Engineers and managers will learn how to leverage automated test-and-measurement, database, and information-management technologies to get valuable information to optimize product performance and testing productivity, and increase quality. Attendees will learn the value of being able to:

Access test data, analysis, and reports instantly
Instantaneously aggregate, analyze and correlate test results
Improve decision-making and collaboration
Optimize design, validation, and verification processes
Gain engineering productivity

Moderator: Rick Nelson, Chief Editor, Test & Measurement World
Presenters: Gricha Raether, Sales and Marketing Director for VI Technology

September 2007

New Approach to Logic Design: A Shift in the Paradigm from Design for Test to Design with Test

Webcast Date: September 26, 2007 1 PM EDT, 10 AM PDT

The business impact of product quality is reflected in key metrics such as time to yield, profit margin, brand equity and customer satisfaction. Achieving and maintaining complex product quality is an increasing challenge as time to market shrinks and performance increases in deep submicron technologies. EDA’s role is prominent has a significant role to play in product quality, including the design of quality in the product from RTL to masks; the validation of product quality as products get tested in the manufacturing floor; going from ‘design for test’ to ‘design with test’ methodology; and the closed loop corrective action loop driven by yield diagnostics.

This webcast will teach you:

How to effectively design, verify and implement fully testable RTL block and chip-level designs with minimal iterations
Improve chip quality, lower test costs and achieve higher yield faster
Develop test programs to address process variations using timing-aware ATPG
Manage the entire process with a metric-driven flow

The A B C-V’s of Accurate Impedance Measurements on Wafer

Webcast Date: September 27, 2007 12 PM EDT, 9 AM PDT

In semiconductor device and process characterization and model verification, wafer-level impedance measurements, particularly C-V measurements, are a necessity, especially in a world of high-k, ultra-thin and low-k dielectrics. Such measurements allow the test engineer to get critical information about the device under test (DUT) such as gate oxide thickness (tOX) and threshold voltage (VT).

There are several different methods for measuring impedance that differ based on the measurement frequency, setup and equipment used. Figuring out which one to use and how to get the best results with that method are significant challenges facing test engineers today.

What you will learn in this webcast:

Trends in impedance measurement
The importance of accurate impedance measurements in the device design and process control activities
Differences among the generally-accepted methods for measuring impedance
Optimizing your wafer-level measurement system for impedance measurements
A few simple tips to immediately increase the accuracy of your wafer-level impedance measurements

Moderator: Rick Nelson, Chief Editor, Test & Measurement World
Presenters: Andrej Rumiantsev, Applications Group Manager, SUSS MicroTec Test Systems

Successfully Negotiating the PCI Express 2.0 Super Highway Towards Full Compliance

Webcast Date: August 29, 2007 2 PM EDT, 11 AM PDT

What do you need to know about new compliance requirements to meet the PCI Express 2.0 standard? PCI Express 2.0 operates at twice the data rate (5.0 GT/s) compared to first generation PCI Express technology. Enforcement of the PCI Express 2.0 standard will soon be required by the PCI-Sig (the governing body of PCI Express) for vendors who wish to have their products listed on the PCI-Sig’s PCI Express Integrators List for PCI Express 2.0. In addition, significant changes in both the physical layer electrical measurements as well as link and transaction layer compliance tests will be instituted.

This presentation will tell you:

What you need to know about those changes
How to validate your motherboard and add-in card device under the 2.0 spec helping to ensure that you will be ready to qualify for the Integrator’s List
Inform you of new electrical, link, and transaction tests and procedures for Gen2
How to ensure your designs are taking maximum advantage of the upgraded throughput offered by PCI Express 2.0

Moderator: Rick Nelson, Chief Editor, Test & Measurement World
Presenters: Rick Eads, Senior Program Manager, Design Validation Division, Agilent Technologies
Gordon Getty, Application Engineer, Logic and Protocol Test Group, Agilent Technologies

Designing good switching modules for ATE systems

Webcast Date: August 15, 2007 12 PM EDT, 9 AM PDT

This tutorial will provide attendees with an understanding of switching systems and the elements in them. It will also describe the discontinuities associated with putting switches in a signal-transmission path. In addition, the Webcast will discuss the techniques used in designing good switching systems and will outline the value of a good driver design that lowers the overall integration cost. It will present examples of common technical problems with switching system design and interfacing and will describe potential solutions.

Topics include:

Typical problems in current ATE designs,
The most overlooked part of an ATE system--the switching,
The Achilles heel in a switch system design,
Problems associated with various types of relays used to make a switch system,
Grounding, and
Different design approaches and their impact on the cost.

Moderator: Rick Nelson, Chief Editor, Test & Measurement World
Speaker: Jeffrey Lum, Chief Technical Officer/President Ascor Division

Register for this FREE Webcast on Designing Good Switching Modules for ATE Systems

Test Coverage Decisions for the Printed Circuit Assembly Factory

Brought to you by ASSET InterTech in partnership with TMWorld.com, this free webcast will discuss how to maximize your test coverage and how this will increase yields, improve quality and shorten time-to-market. Given those and other benefits, why is 100 percent test coverage virtually impossible to achieve? And if full test coverage is unachievable, how do you get as close as possible?

Speaker: Arden Bjerkeli, Director of Customer Applications Support, ASSET InterTech
Moderator: Rick Nelson, chief editor of Test & Measurement World.

View this one-hour webcast or download the slides and find out how a skillful selection of test technologies can approach full assembly and functional test coverage.

Register now for this free webcast or download slides here
View reference links and recommended readings related to how to maximize your test coverage here

Finding and Troubleshooting Intermittent Signal Faults

Test & Measurement World and The EDN Network in partnership with LeCroy presented a free Webcast covering the best practices for using digital oscilloscopes to identify and troubleshoot intermittent signal failures. The Webcast also covered how you can identify the source of intermittent failures when performing eye-pattern testing or jitter measurements.

Speaker: Dr. Mike Lauterbach, director of product management for LeCroy.
Moderator: Rick Nelson, chief editor of Test & Measurement World.

Enterprise Test Management for Electronic Component and Device Designers

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