How DFT conquers chip complexity (continued)
A continuation of our interview with Antun Domic, VP and GM of Synopsys, which appeared in the June 2008 Viewpoint column.
Larry Maloney, Contributing Editor -- Test & Measurement World, 6/1/2008 2:00:00 AM
Q: How important is DFT among semiconductor manufacturers?
A: Given the complexity of chips being designed today, every semiconductor company knows how vital DFT is to ensuring product reliability. You don’t see people debating whether they need to have scan design or BIST [built-in self-test] for memory. Company goals in implementing a test strategy reflect three chief concerns: high test quality to cover all defects, simple processes that avoid extra steps in chip design, and cost control. The best way to accomplish all these objectives is to implement a DFT strategy at the very beginning of the design process.
Q: To what extent does the globalization of semiconductor design further complicate these test challenges?
A: The challenges relate not so much to test but to overall design. For example, you might receive a component of your chip that was designed by another team in a different location. To ensure quality in the overall design, you need to implement very explicit DFT strategies that apply to all the engineers involved with that chip design—no matter where they are. Certainly, you want to preserve the diversity of design approaches and take advantage of talent everywhere. But at the same time, you need to have discipline in the DFT plan. When you receive a chip component from another location, you need to know what to expect in the way of scan chains or compression strategy.
Q: What are the primary tools in the Synopsys Galaxy suite for engineers who want to get started in addressing DFT issues?
A: DFT Compiler allows design engineers to very easily generate scan chains while they are synthesizing their designs. Integration into the design flow means that designers will not need to iterate the flow because of DFT issues. In short, DFT Compiler “predictably” incorporates test into the design.
Also integrated into the design flow is our BSD Compiler for generating boundary scan, manufacturing test patterns, and BSDL files for board-level tests. BSD Compiler does all this while requiring little to no knowledge of boundary scan. Finally, as noted earlier, our newest and most advanced tools include DFT MAX for compression and TetraMAX.
Q: What is the typical learning curve for engineers seeking to master these products?
A: It’s hard to put a time estimate on this, but experience with our training classes shows that it takes only a few days to learn these tools. A big reason is that we took the opportunity to uniquely integrate our DFT solution into our synthesis solution, Design Compiler. As a result, putting standard scan into many designs requires setting just one switch. Because most designers are already using Design Compiler with DFT Compiler scan insertion, using DFT MAX for compression is a small, incremental step. Most customers tell us that they are able to start using DFT MAX within a day.
And turning to TetraMAX ATPG, that tool is ready to generate patterns immediately after the design is finalized. Customers can run it right away because DFT MAX automatically creates the setup file for TetraMAX ATPG.
The bottom line on all this is that we have not heard comments from engineers like “we would really like to use compression, but it is so complex that we’re going to skip it.” We have succeeded in lowering the barriers. Once people see the benefits, they adopt the technology quickly.
Q: What are some of the educational approaches that you’re using for test automation?
A: There’s quite a variety, including formal training programs, informal lunches to acquaint customers with our products, and extensive field support. The SolvNet feature on the Synopsys Web site is the engineer’s entry point to all sorts of support articles, software releases, and downloads. It’s also where customers can open an ongoing support case. Customer Education Services provides online training for all of our products, including DFT. And for each software release, there is online update training on SolvNet.
Interest in our Synopsys Users Group (SNUG) is growing as well. In April, a record-breaking 2032 users attended SNUG San Jose, a 29% increase over 2007 attendance. And as evidence of the growing interest globally, our users group meeting in India last year drew more than 1500 attendees.
Q: Where do you see the greatest use of Galaxy Test products among engineers?
A: We see usage all over the world, because advanced companies are also global companies. Take a company like Texas Instruments. Many of its designs originate both in North America and in India.
If I were to you give some general impressions, I would say that IC designers in the US seem to be focused more on performance issues. So, concerns over such issues as small delay defects first surfaced in the US.
If I look at who is putting emphasis on cost-saving techniques, such as higher compression, you see a great deal of interest from manufacturers of chips for consumer-oriented products, particularly companies in Japan and Asia Pacific. The costs of test are amplified with high volume, and therefore compression can yield noticeable tester savings. Among the many companies that have adopted DFT MAX is Korea’s LG Electronics, which has deployed this scan-compression tool to increase test quality in 65-nm chip designs for HDTV.
So, there are regional differences, but even so, I would have a hard time telling you which geographic region is the biggest user of products such as DFT MAX.
Read the first part of this interview.
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