Best in Test Finalists: EDA/DFx/Test data-analysis software
-- Test & Measurement World, 12/22/2008 2:00:00 AM
→ DFT MAX compression solution, Synopsys
→ Encounter True-Time ATPG, Cadence Design Systems
→ Global Test Operations Solution, OptimalTest
→ Solder Joint Built-In Self-Test Software, Ridgetop Group
DFT MAX compression solution
Synopsys
www.synopsys.com
DFT MAX is a test-compression solution that addresses silicon manufacturing test costs and quality challenges occurring in 130-nm, 90-nm, and smaller process technologies. It delivers pushbutton 10X to 100X test-data and test-time compression, along with design-rule checking including scan, boundary scan, test-compression synthesis, integration, and verification capabilities. The 2008.09 version of DFT MAX tackles the increasing problem of excessive power consumption at the tester.
Scan-based manufacturing patterns often exceed the mission-mode power budget. The corresponding IR drops in the device cause the test program to fail and result in non-defective parts being thrown away. In other cases, engineers spend days or weeks debugging the power-related tester program problems.
DFT MAX compression conquers this power problem by allowing users to dial in a power budget. It generates patterns that ensure that the power at the tester is within this budget. Customers are currently using these capabilities on silicon with beneficial results—and without any design changes.
Prices for DFT MAX start at $147,000 for a one-year subscription license.
Encounter True-Time ATPG
Cadence Design Systems
www.cadence.com
The latest version of the Encounter True-Time test platform supports multiple on-chip compression architectures as well as gate-exhaustive and power-aware test pattern generation. With compact, high-coverage, high-quality sets of manufacturing tests, engineers can reduce cost of test and ensure quality of silicon.
Encounter True-Time ATPG (automatic test pattern generation) offers a method for improving quality at lower cost through a pattern fault-modeling capability, where pattern faults are defined as a stuck-at fault with logic-value constraints on a set of nets. This capability is used to specify a more comprehensive fault list in terms of exhaustive gate input combinations (or gate-exhaustive modeling) and corresponding gate output stuck-at faults for all gate and cell type faults.
ATPG engines generate tests for all standard design-for-test methods, styles, and flows. Encounter True-Time provides intelligent ATPG with compression to reduce scan test time, while maintaining high test coverage for the complex manufacturing defects common in devices built using process technology at 90 nm and below. Its low-power test capability also mitigates the costly impact of average and instantaneous test-mode power consumption on yield and product reliability.
Base price for Encounter True-Time is $65,000.
Global Test Operations Solution
OptimalTest
www.optimaltest.com
Global Test Operations Solution, test-management software for fabless organizations and IDM business units that outsource, provides a single integrated view of global test operations and processes, vertically within an organization or dispersed among subcontractors, in real time, in near time, and offline. It offers an enterprise-wide, unified IT backbone for semiconductor test, allowing users to monitor, control, and manage increasingly distributed manufacturing functions, from wafer sort to final test.
The turnkey system offers such features as centralized databases with rapid data retrieval and adaptive testing coupled with a methodology for establishing reference (base-line) dies. It also provides an open, flexible algorithm engine; smart datalogging; the ability to track consignment hardware; and a high degree of automation, all focused on test.
Global Test Operations can be implemented in different phases and with different options. OptimalTest can install its station controllers at subcontractor locations or obtain their datalogs (in any format) for transfer to local or regional operational centers for near-time delivery of early notifications about quality, yield loss, test time control, and data integrity. Offline, datalogs can be transferred from regions to headquarters for additional early notifications, offline analysis, and global reporting.
Annual software licenses, which take into consideration the size of the implementation and added features, start at $150,000.
Solder Joint Built-In Self-Test Software
Ridgetop Group
www.ridgetop-group.com
Comprising a Verilog soft core that is synthesizable into a customer’s FPGA, Ridgetop’s SJ BIST provides real-time detection of solder-joint faults in programmed FPGA devices. It detects and reports troublesome intermittencies and BGA (ball-grid array) failures to prevent catastrophic faults in electronic control systems.
Solder joints used by BGAs are subject to mechanical failure. They inevitably suffer damage from thermal and vibrational stresses, causing hard-to-find intermittent connection problems between components on printed-circuit boards. SJ BIST’s ability to measure, detect, and predict solder aging and the resultant failure of electronic modules is an advancement in electronic reliability.
SJ BIST has been independently validated by automotive and aerospace firms on multiple FPGAs and BGA packages and in multiple applications. It is supplied as a synthesizable Verilog IP core, with prices starting at $9900 for an evaluation license and full support.
| Go back to the complete list of Best in Test finalists. |
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