How DFT conquers chip complexity
In a recent interview, Antun Domic of Synopsys discussed the role of design for test in curbing costs and ensuring reliability in IC design and manufacture.
By Larry Maloney -- Test & Measurement World, 6/1/2008 2:00:00 AM
Q: Is design for test (DFT) strictly the domain of DFT engineers?
A: Certainly, there are DFT specialists, and their responsibility is to construct the DFT strategy for the chip. But verification engineers also need to understand DFT, since they must verify the chip functionality in its test mode. As for design engineers, we see that users of our Design Compiler tool—traditional logic design engineers—also run DFT Compiler and DFT MAX, our scanning and compression tools. We’ve made these tools part of the design flow, so these engineers don’t have to call in test experts.
Antun Domic addresses more questions on DFT, including regional needs among engineers, in the continuation of this interview. |
Q: What impact is growing IC complexity having on test?
A: One example is that you can have a path with no defects from the standpoint of functional failure. An increased resistance on a via will make the node switch, but the delay is going to be much longer, resulting in a small delay defect. Another growing concern is power consumption. As engineers reduce power consumption on chips, they are designing thinner power and ground lines. As a result, testing can stress the chip with an amount of switching that can cause a failure. So, a new challenge is how to keep the pattern count low and the coverage high while reducing power consumption.
Q: What are your key tools for addressing new test challenges?
A: Our DFT MAX automatically implements “adaptive scan,” the Synopsys version of scan compression, on chip hardware to reduce the amount of test data. Companies need this technology for two reasons: First, testers have a finite amount of memory to retain test patterns, and second, customers want to limit the time spent by the tester on each device. If test patterns exceed the tester memory limit, they are cut back, which lowers test quality, ultimately resulting in higher service costs. You can add memory, but this increases costs. At our San Jose user conference, RFMD, a supplier of wireless components, reported projected savings of $25 million from using DFT MAX.
Q: How about improvements in automatic test-pattern generation (ATPG)?
A: Advanced fault models are driving ATPG to produce higher test quality. For example, small delay defects associated with nanometer processes can adversely affect timing-sensitive paths, leading to circuit failures. Standard transition-delay ATPG lacks sufficient timing resolution to create tests that reliably detect these small delays. The Synopsys TetraMAX solution, however, can process precise timing information from the PrimeTime suite to generate small delay defect patterns and identify subtle defects that were previously undetectable.
Q: Moving forward, what will be your key focus in DFT technology?
A: Early this year, we announced that our IC Compiler was used in a 45-nm system-on-chip device from Matsushita. The size of this chip was over 250 million transistors. So, customers clearly are planning larger designs. This means we’ll need to make more strides in compression to extend tester life.
More gates on the chip also require greater capacity and faster run time, which we’re addressing in all our tools, including test. Customers want to reduce power in test-pattern generation. As we move to smaller chip geometries, such as 32 nm, we’ll need to respond to defects related to small delays and other issues.
Finally, there’s the challenge of design flow. For example, the more compression you do, the more problems you have in place and route because of more congested circuitry. We must always make sure that overall design productivity is not compromised by test requirements.
Read the continuation of this interview.
How DFT conquers chip complexity (continued)
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