Guest commentary: FPGA design for portable T&M gear
A complete version of Charlie Jenkins' Test Digest article, which appeared in our March 2007 issue.
Charlie Jenkins, Altera -- Test & Measurement World, 2/28/2007 11:18:00 AM
Click here to see the original article from the March 2007 issue.
The electronics world is rife with test-and-measurement standards, and the list continues growing. Almost every consortium and government agency has a lengthy list of mature, new, and emerging standards. Some of the more notable consortiums are the IEEE, FCC, JEDEC, ITU, and OIF.
Traditionally, test-and-measurement OEMs have focused their product designs on performing specific test procedures based on a solitary standard. As a result, OEMs have been forced to bite the bullet and dole out substantially large design engineering resources to produce new products that perform the necessary testing based on each and every new and revised standard.
The mere fact all products have to be tested prior to shipment to end customers is the dynamic driving the pervasive nature of the T&M business. This includes the broad categories of communication, semiconductor/automatic test equipment (ATE), and general-purpose test. Under these categories, there are long lists of different types of testers, large and small. However, a definite T&M trend is toward greater portability to increase productivity and reduce capital outlay.
Field programmable gate arrays (FPGAs) continue to make major inroads in the growing universe of portable T&M gear, thanks to ever-increasing on-chip functionality, flexibility, and highly efficient FPGA design tools. The flexibility inherent in a FPGA-based portable T&M design gives developers the golden opportunity of creating a single hardware design that can serve as the basis for multiple and differentiated products, thus reducing manufacturing and time to product costs. That’s made possible by the programmable platform that uses FPGAs. This platform allows product developers to rapidly develop new capabilities and, by utilizing the reprogrammability of FPGAs, easily incorporate them into their design to reach the market in the shortest amount of time.
An FPGA integrates into a single chip the majority of the functionality traditional component collections provide. The CPU, user-interface controllers like LCD and touch panel, ASSP controllers for DSP functions and battery management, the glue logic, and the communications interfaces can all be implemented using intellectual-property (IP) cores available from the FPGA vendor.
A single FPGA design can support a variety of T&M feature sets. Plus, FPGA-based portable test gear can be upgraded in the field as new test standards or revisions of older ones are put into practice. An OEM’s ability to add or modify FPGA-based test functionality many years after the initial design protects T&M customers against product obsolescence and is critical for success in the test industry. In a similar manner, the automobile industry has successfully and profitably relied on this same “design once, make many” philosophy for many years.
By taking this route, T&M OEMs can significantly reduce product design costs, streamline new designs, stay abreast of T&M standards, provide customers with timely, cost-effective products that deal with a host of current standards, and all the while, remain competitive and profitable.
A hardware platform can contain an FPGA that implements all the functions common to portable test devices, such a central processing unit (CPU), display drivers, keypad interfaces, and generic input/output ports. Specific test designs can then augment this platform with whatever elements are unique to the device, such as analog I/O channels and DSP processing blocks. Reprogramming the FPGA will then take care of required variations in specific functions such as display size and resolution and number of keys, allowing the basic hardware platform to remain unaltered.
Accelerating Product Development
When the T&M OEM adopts an FPGA-based hardware platform, a good starting point for the initial platform is a reference design for portable systems from an FPGA vendor. These reference designs accelerate time-to-market for new designs because they have already been validated and are provided with full board fabrication details. Also, reference designs typically offer a library of fully-integrated FPGA cores that are tuned to the needs of a T&M portable system.
In some cases, developers want to retain their software investments in specific processor technologies as they move to an FPGA platform design. In those instances, they can retain the CPU they have been using and implement all remaining circuitry in an FPGA. However, they will realize the ultimate benefits of size, power and cost, by integrating all the logic functions of a design into the FPGA.
System designers are now getting major assistance with portable reference platforms (PRP) from FPGA vendors such as Altera, which accelerate product development. The figure shows the PRP composed of a software processor development board, display imaging board, and VGA video controller board. A number of demonstration applications have been developed to run on this platform.
 |
| The portable reference platform (PRP) comprises a software processor development board, display touch panel board, and VGA video output board. |
The platform demonstrates the use of software productivity tools, embedded processors, and system-on-a-programmable-chip (SoPC) design tools to rapidly embed LCD, touch panel, and CMOS imaging IP cores in an FPGA. Also, IP blocks such as hardware accelerators and image edge detectors are included to give designers an understanding of the FPGA’s DSP and co-processing capabilities.
As part of this PRP, designers can use tools such as SoPC Builder to effectively integrate the necessary electronic building blocks, including their own IP, and automatically configure the FPGA interconnects. By integrating these functions into an FPGA, the power issue is efficiently addressed. A single FPGA uses less power than a collection of separate chips, as has been the case historically. Deploying portable test functionality on an FPGA also provides an opportunity to implement dynamic power management, further reducing system power.
Table 1 shows the design metrics of this PRP. An implementation of a touch panel and LCD controller design, which took two and five days, respectively, is included to jumpstart the user. Integration with other IP blocks can be performed in minutes using the SoPC Builder tool, which automatically generates the interconnect fabric between all functional modules. Further, thanks to the computational power of Nios II embedded processors in the FPGA and the C2H (C code to hardware) tool, hardware accelerators for software algorithms like Mandlebrot fractal can be sped up to 10,000 times, by moving them into dedicated custom hardware accelerators (Table 2).
Providing Market Flexibility
As a result of continuing integration and advanced semiconductor process technologies, earlier desktop, plug-in T&M products are rapidly moving to portable, handheld versions. Here is where FPGAs make major contributions. An FPGA-based design strategy can meet OEM challenges at various stages of a product’s life cycle. Those are the concept, emerging-market, aggressive-growth, or mature-market stages of a portable T&M product.
At the concept level of product development, engineering wants to know if its “great” product idea can be a viable market entity. Engineers can prototype their concepts based on an FPGA design at a fraction of the development cost and time compared to traditional design approaches. In the mature-market stage, FPGAs can be used to incorporate slight feature differentiation to ASSP product or to mimic the functionality of ASSPs that are no longer in production. T&M product OEMs can exploit tactics like these to help maintain volume and price when the portable T&M device has matured and market growth slows.
Automotive test
Automobile testing provides a classic example of the versatility of an FPGA. Extensive testing with a variety of different test procedures is involved, and in these instances, auto test engineers use an assortment of different test gear. Test examples include simple temperature measurements to verify climate-control functionality, monitoring in-vehicle networks to assure all electronic functions properly communicate with one another, and acceleration measurements to assure a smooth ride.
Instead of stockpiling many diverse auto test instruments, automakers can opt for a single FPGA hardware platform to provide solutions to these and many other in-vehicle test applications. Auto test engineers can use an FPGA-based portable device for one particular test application--for example, low-speed GPS or temperature logging—and then, as another example, expeditiously reprogram the portable device on the spot to comply with high-speed sampling rates required for crash tests. Moreover, they can configure their portable devices to perform both low- and high-speed measurements in the same handheld system to implement multiple tests in parallel.
While auto testing gives the impression there are endless numbers of different tests, consider the area of noise, vibration, and harshness (NVH) testing that accounts for hundreds of different tests and cuts a wide swath through a multitude of industries. According to recent Frost & Sullivan research, NVH test gear includes analyzers, shakers and controllers, accelerometers, noise dosimeters, octave-band filters, transducers for vibration and acoustics, dynamometers, sound level meters, microphones, and analysis software.
These tests are applied to a plethora of applications such as testing of engine noise vibration, acoustic performance, sound power, pass by noise, noise field mapping, occupational health and safety, structural dynamics, and vibration testing.
Specific examples like auto and NVH testing are further evidence that a single FPGA-based platform can save T&M OEMs vast amounts of engineering dollars by relying on an integrated yet flexible platform that yields a variety of different tests in one product. When test requirements change, test engineers simply download new code to their FPGA-based portable test devices. This eliminates the need to wait for new custom hardware to comply with new standards.
Furthermore, in some cases, portable system designers may require a low-risk, cost-reduction path for high-volume production. To make this happen, designers can migrate their FPGA designs to a structured ASIC, like Altera’s HardCopy, that can offer up to a 70% cost reduction.
Wasteful efforts through conventional design
To date, portable test devices have generally been designed the old-fashioned and expensive way, using multiple discrete components and a standalone CPU. Traditional design like this incurs considerable engineering resources to implement custom hardware platforms. And consider that each and every time standards change, a custom hardware platform is designed for specific test procedures to comply with those specific standards. Without question, this results in wasteful efforts developing standard blocks instead of custom application blocks that can cost-effectively be used over and over again. Also, the T&M OEM runs the risk of discrete ASSP and CPU component obsolescence, as well as integration risk, cost, and inflexibility of ASICs.
T&M OEMs harboring these less-than-efficient design practices are learning that engineering productivity improvements lie squarely on an agile product development process. ASSPs and ASICs provide a low-cost, fixed platform for product design. There are however downsides to using these devices. Product differentiation is difficult with ASSPs. Plus, these devices are not always available for the most current test standards and logic functions and may be prematurely obsolete over the product’s lifetime.
Custom ASIC development, on the other hand, can be time-intensive and costly. Non-recurring engineering (NRE) costs can easily exceed $1M, as well as incur year-long development cycles and the need to wait for silicon re-spins for design changes. By adding FPGAs to this design mix, however, a new level of flexibility emerges. For instance, ASICs or ASSPs can be used to deliver the basic system functionality. To quickly incorporate the latest in-demand features to a portable test product design, low cost FPGAs complete the programmable platform for product development.
Table 1. Subsystem design effort|
Subsystem |
Logic elements |
Memory (bits) |
Multiplier (9 x 9) |
Design effort |
|
LCD controller design |
511 |
12,800 |
-- |
5 days |
|
Touchpad controller design |
200 |
-- |
-- |
2 days |
|
Video in |
1044 |
38,400 |
16 |
0* |
|
I2C |
198 |
-- |
-- |
0 (open cores) |
|
Algorithm engine |
578 |
-- |
24 |
0 (reusable IP reference design) |
|
DMA engine |
613 |
-- |
-- |
0 (reusable IP reference design) |
|
SOPC integration |
-- |
-- |
-- |
Minutes |
|
System debug |
-- |
-- |
-- |
5 days |
*The design is described in Altera Application Note AN 373, “Avalon Video Input Module” (http://www.altera.com/literature/an/an373.pdf)
Table 2: Acceleration factor
|
Floating-point software |
Integer software |
Accelerator hardware |
DMA I/O offload hardware |
|
Pentium @ 1600 MHz |
30 ms |
110 ms |
N/A |
N/A |
|
Pentium @ 75 MHz |
640 ms |
2347 ms |
N/A |
N/A |
|
Nios @ 75 MHz |
351,789 ms |
243,017 ms |
211 ms |
35 ms |
|
Column to column Nios acceleration factor |
-- |
1.4X |
1152X |
6X |
|
Cumulative Nios acceleration factor |
-- |
1.4X |
1600X |
9700X |
Click here to see the original article from the March 2007 issue.
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