Relationships key to boundary-scan success (continued)
-- Test & Measurement World, 10/1/2005 1:59:00 AM
A continuation of our interview with Glenn Woppman, president, CEO, and Chairman of the Board of Asset InterTech, which appeared in the October 2005 Viewpoint column.
Click here to read the first part of the interview.
T&MW: Could you elaborate on relationships?
Woppman: We see them as really critical, and the ability to maintain relationships is what we consider as a core competency of our company. First, we establish good relationships with our customers to help them get as much coverage as they can from their boundary-scan tests. If they want to avoid building test fixtures, we can work with them and maybe find a way to extend JTAG coverage close enough to 100% that they don't need to build a fixture. In addition, our customers are driving where their technology is going, so they help us determine where we should make investments and how we should prioritize our resources to get the biggest bang for our investment in product development. That brings up a second set of relationships, and that's with partners who offer complementary test technologies.
For example, we've teamed up with International Test Technologies so we can combine its microprocessor emulation capability with our JTAG test capability. A customer might have a microprocessor board that contains a non-JTAG Ethernet controller. We might not be able to provide a net-by-net report, but the microprocessor can talk to the controller, and JTAG combined emulation might well provide an adequate test without the expense of fixturing. And of course, to serve customers who do require ICT, we've partnered with Agilent Technologies.
And finally, of course, we maintain good relationships with the semiconductor makers, who are the lifeline that enables this market.
Because those external relationships are so key, internally we have to have a company culture that ensures our people are empowered to foster good relationships. Some companies have that not-invented-here factor--that doesn't exist at Asset. If we invent something, great, but if someone else has a good idea, then we will work with him to get test solutions to our customers fast.
T&MW: How important are relationships between Asset and in-circuit test vendors?
Woppman: In the beginning, we were mutually exclusive. Boundary-scan tools like ours found use in development, and the ICT guys put their own boundary scan on top of their systems. But as boards became denser and more boundary-scan chips became available, people wanted to reuse their prototyping tests in production, and our tools started becoming complementary to ICT. An example where this approach is getting traction is Microsoft's Xbox. Xbox designers use ScanWorks for prototype development, and the ScanWorks tests get reused on Agilent 3070s at the Asian contract manufacturers that build Xboxes. We have at least 10 other customers that this year have deployed a similar reuse model.
T&MW: What are the typical challenges that users face when first applying boundary scan?
Woppman: In the design community, you'll find a lot of risk takers designing gigabit-rate buses and so on. These people recognize that a new technology might not be perfect, but they're willing to adopt it and make it work. The test community, on the other hand, tends to be risk averse. Test engineers need to test and ship products, and revenue is on the line. If they reach out for a new technology and can't make it work, they can't ship product. Our customers are maybe 40% in the risk-taker side and 60% in the risk-averse side. We try to help both sides; first, by offering advanced capabilities for the power-user risk-takers, and second, we have an extensive program of support services for the risk averse.
T&MW: Are semiconductor vendors doing a good job of providing boundary-scan-compatible chips with quality BSDL files, and are there any additional steps these vendors should be taking?
Woppman: It's an ongoing process that continues to get better but at an incremental pace. I've already talked about DFT and risk issues as challenges. I'd put BSDL quality third. As chip designers begin using the JTAG port more and more to debug their own chips, things will improve as they learn that a quality boundary-scan implementation will help them as well. In the past, JTAG has benefited primarily the board designer, and the chip designers took their eye off the ball once in a while. The situation is in pretty good shape, but I always want it better, because if it's in really good shape, my market grows faster.
T&MW: Are universities addressing boundary scan?
Woppman: It's ad hoc. Some professors have the viewpoint that test is important and will take the initiative to cover it. We have our tools at a scattering of universities, but you won't find university programs built around boundary scan like the ones built around DSPs.
T&MW: What has changed in boundary scan since its adoption as a standard?
Woppman: When the technology was first envisioned in the mid-1980s, it really targeted the problem of providing structural tests despite limited physical access. But the JTAG people were open-minded and made the standard flexible enough to permit extensions. Consequently, boundary scan has evolved to cover not just structural test but to become the key access mechanism into silicon IP to do many different things. In the mid-1990s companies like Xilinx, Altera, Lattice Semiconductor, and Atmel began supporting in-system programming via boundary scan, and microprocessor makers began putting full-scan implementations in their DSPs, Pentiums, and PowerPCs. Now, Freescale has boundary scan in its 16-bit and even 8-bit microcontrollers.
The flash-memory makers haven't put boundary scan directly in their devices, but they have done a lot of work to permit programming via boundary-scan devices adjacent to flash chips. Now, we are beginning to see boundary-scan applications for debugging system-on-chip devices, which might include multivendor cores that each have a JTAG port. Finally, we are seeing boundary-scan applications for high-speed buses, possibly in conjunction with Intel's iBIST [interconnect built-in self-test] technology. LogicVision has developed IP for Serdes BIST, and that might play well with dot-6. We think the dot-6 is a little more rigorous on helping with the structural test, whereas BIST might be more suitable for the design-validation side. So, we think these two could be very complementary.
T&MW: What are the prospects for analog boundary scan?
Woppman: Questionable. We've had the 1149.4 standard for a while, and to its credit, National Semiconductor has developed a dot-4 chip that lets people learn about the technology, but we don't see momentum building.
T&MW: What's the future of boundary scan?
Woppman: What has impressed me are the trends in base-level technologies and the fact that they are moving in a direction that enables my market to grow. Of course, boundary scan as originally defined in the 1149.1 standard is primarily a DC shorts and opens technology that's not suitable for AC-coupled higher speed buses, and you could argue that 1149.6 cannibalizes the fundamental boundary-scan test market. But in fact, what it does is leverage the access capability of the original standard. We are not pigeonholing DC boundary scan and saying, well, that doesn't work here and we need to replace it with something totally different. We are letting it evolve.
In contrast, ICT is facing limitations. You have the limited access, and chips are starting to consume so much power that you might not even be able to populate a board under test with a microprocessor and power it up for ICT. Now, many people have predicted ICT's demise, but I don't know when the heck that might ever come. In fact, it is still a critical test technology. But I think we can agree that there's no dynamic that points to huge market growth for ICT and MDAs.
T&MW: But for boundary scan?
Woppman: Right now, the future is looking pretty bright.
Click here to read the first part of the interview.
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