RTL approach supports memory BIST and repair insertion
Traditionally, you would implement MBIST and repair functionality for SOC designs at the gate level. But now you can use an approach that inserts MBIST and repair at the RTL.
Rick Nelson, Editor in Chief -- Test & Measurement World, 8/1/2009 2:00:00 AM
SOC (system-on-chip) designs often incorporate multiple instantiations of various types of memories, including single-port, double-port, and content-addressable memories of various sizes and cuts. In addition to the memory itself, a memory provider also supplies the IP (intellectual property) necessary to implement memory BIST (built-in self test) and—for redundant memory—repair.
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The SpyGlass-MBIST insertion tool supports a bottom-up flow where the memories in lower-level blocks are replaced with BIST-enabled memories. Read a paper from Atrenta that describes the use of the company’s SpyGlass-MBIST tool to insert “vendor independent” MBIST IP at the RTL in Verilog or VHDL. |
Traditionally, you would implement MBIST (memory BIST) and repair functionality at the gate level. But now you can use an approach that inserts MBIST and repair at the RTL (register transfer level). The approach is independent of BIST IP technology and works with any supplier’s qualified ASIC design kit and BIST libraries.
The approach offers several benefits when compared with MBIST insertion at the gate level. For example, with gate-level insertion, functional verification will take longer, and any optimization you perform during synthesis and early floor planning will not optimize the MBIST logic you later insert at the gate level. In contrast, with MBIST inserted at the RTL, you can perform mission- and test-mode verification at the RTL, and you can minimize iterations between RTL and gate-level design.
In the white paper “A Register Transfer Level Approach to Memory Built-in Self Test and Repair Insertion,” Dr. Aloke Das and Kiran Vittal of Atrenta describe the use of the company’s SpyGlass-MBIST tool to insert “vendor independent” MBIST IP at the RTL in Verilog or VHDL. They note that the approach has been deployed at customer environments based on qualified libraries supplied by the ASIC vendors. The SpyGlass-MBIST insertion tool supports a bottom-up flow where the memories in lower-level blocks are replaced with BIST-enabled memories (figure).
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