Tester per pin for systems on a chip
A family of SOC testers designed to meet volume test challenges has received our first Test of Time Award.
Rick Nelson, Chief Editor -- Test & Measurement World, 3/1/2005 2:00:00 AM
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Read other articles from this issue:Table of contents, March 2005
AWARDS Test Engineer of the Year, Cover Story Test Product of the Year Test of Time OTHER FEATURES Reduced pin-count test Improving sensor reliability Bits battle noise Picture Perfect |
Hewlett-Packard Company today unveiled a family of semiconductor test systems that are designed specifically to meet the volume production test challenges of today's highly integrated System On a Chip devices." So noted the July 14, 1999, press release that introduced the 93000 SOC Series semiconductor test system.
Since its introduction, the 93K has gained some gigahertz, the Agilent Technologies moniker, an impressive array of instrumentation, and satisfied customers, all the while preserving and building upon its innovative tester-per-pin architecture.
The combination of innovation and customer acceptance have earned the 93K Test & Measurement World's first annual Test of Time award, created to recognize a product line that continues to provide state-of-the-art performance for at least five years after the initial introduction.
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| Introduced in 1999, the 93K now offers 3.2-Gbps digital performance—with rates to 10 Gbps supported on selected pins—and an array of instruments such as Audio/Video 8 for parallel multisite analog test and BIST Assist 6.4 for 6.4-Gbps serial I/O test. |
According to Tom Newsom, VP and GM of Agilent's SOC Business Unit, the incentive for developing the 93K was to "stop inventing logic testers on the one hand and mixed-signal testers on the other" and to invent a single platform that could accommodate the combined analog and high-speed-logic test needs of emerging SOCs. It's been a winning strategy: Agilent has shipped more than 900 of the 93K systems, Newsom said, to customers including all of the top 10 semiconductor manufacturers. Several customers, he said, have more than 100 units.
But a winning strategy is unlikely to be easy to implement. Hans-Juergen Wagner, managing director, R&D and marketing, Germany, explained that developing the 93K as a platform for SOCs presented "a combination of many challenges—the architecture, the integration, the shielding, and the power system." The tasks were particularly daunting because of a lack of clear definition for what an SOC was, he added. The 93K's developers knew they needed at minimum to pack analog and digital test capabilities into a compact system. Liquid cooling helped shrink the footprint, but the compactness in turn meant that noisy high-speed digital test circuitry would reside near sensitive analog instrumentation.
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| According to Hans-Juergen Wagner, developing the 93K system presented many challenges related to architecture, integration, shielding, and power distribution. |
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| Tom Newsom explained that the 93K’s designers wanted to invent a single platform that could accommodate the combined analog and high-speed-logic test needs of emerging SOCs. |
The tester-per-pin architecture was instrumental in minimizing noise. Traditional testers had a single clock-distribution system, explained Newsom, but the 93K includes a locally generated clock per pin and the necessary localized intelligence to minimize backplane communication. "Analog and digital domains coexist quite nicely," he said, "and we have even dropped in RF as well." The power-system design also helped control noise, said Wagner, who explained that system-level power is distributed at very high voltage levels, then transformed and filtered locally to minimize the effects of loops and other potential noise sources.
Today, the 93K has evolved from a 1-Gbps system to one offering 3.2-Gbps digital performance, with rates to 10 Gbps supported on selected pins. It has gained instruments such as the Audio/Video 8 (for parallel multisite analog test) and BIST Assist 6.4 (for 6.4-Gbps serial I/O test), each of which was introduced in 2004, with more innovations on the horizon.
"I feel even better with our architecture going forward," said Wagner, explaining that it's well-suited to support more pins, higher speed, and better accuracy while remaining flexible enough to handle emerging SIP and other devices, whatever their specific test needs may be.
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