Challenges run gamut from timing to DFM
Rick Nelson, Chief Editor -- Test & Measurement World, 10/1/2006 2:00:00 AM
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Test engineers can expect to confront RF, memory, and compression-based-scan test challenges; perform timing measurements; deal with manufacturability and yield issues; and contend with soft errors. That observation is based on the line-up of new full-day tutorials planned for the International Test Conference, which will be held during the week of October 22 in Santa Clara, CA.
Six new advanced tutorials and one on test fundamentals will complement 10 updated sessions, bringing the roster to 17 total tutorials scheduled for Sunday and Monday, October 22 and 23.
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The ITC has added seven tutorials to the line-up it offered in 2005. Courtesy of the International Test Conference. |
ITC program committee member and ARM fellow Rob Aitken, who heads up the tutorial effort, said in a phone interview that the new tutorial on test fundamentals will meet the needs of 30% of attendees at ITC. Other tutorials will bring test veterans up to speed on emerging topics like RF design for test (DFT), for which a session will discuss how to extend techniques developed for mixed-signal test to the RF domain.
A tutorial on design for manufacturability (DFM) will demonstrate that DFM and yield issues are no longer the exclusive domain of designers. Said Aitken, “The final arbiter of yield is always test, so the interaction between them has to be understood.” Yervant Zorian, chief scientist of Virage Logic, is one of the presenters of the DFM session, which will complement a DFM and yield workshop that Zorian has organized for October 26–27.
A tutorial on memory test might seem to cover old ground, but, said Aitken, what’s new is that DFT engineers now must place test and repair circuitry on hundreds or thousands of memory blocks within 90-nm or 65-nm designs. “The purpose of the tutorial is to give a practical description of the issues involved and the tools available to help.”
Other topics include digital timing measurement. “Test engineers are going to spend a lot of their time with oscilloscopes and other instruments trying to debug their devices and their tests,” said Aitken. Another session will cover soft errors, which, he said, will occur not just in memories but in standard logic as well, as designs move toward 45 nm. Finally, a session on compression-based test will describe how to detect, analyze, locate, fix, and log failures based on compressed data.
Participation in the tutorials earns credits toward an IEEE Computer Society Test Technology Technical Council Test Technology Certificate.
In addition to the tutorials, ITC will feature lectures—essentially mini tutorials—interspersed throughout the technical program. One called “Test Experiments and Case Studies” has this goal, according to Aitken: “By giving people the 'Science 101’ about how to conduct a test experiment, we’ll have more and better trained experimenters conducting more and better experiments and publishing their results at ITC. So, the whole community wins.”
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New tutorials for ITC 2006 |
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Semiconductor Test and DFT Fundamentals |
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Design for Testability for RF Circuits and Systems |
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Design for Manufacturability |
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Memory Test Challenges—BIST and other DFT Techniques |
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Digital Timing Measurements—From Scopes and Probes to Timing and Jitter |
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Soft Errors: Technology Trends, System Effects and Protection Techniques |
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Debugging Compression-based Tests |
| References |
| See a transcript of my interview with Aitken. |
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