Simulate, emulate, or hope for the best?
By Ron Wilson, Executive Editor, EDN -- Test & Measurement World, 4/1/2009 2:00:00 AM
 Three different approaches to blending simulation with in-circuit debug show the variety of verification flows that teams are using today. |
Once upon a time, you verified a logic design for an FPGA (field-programmable gate array) by compiling it, loading it, and pushing the reset button on your evaluation board. But as FPGAs have become larger, this “Blow-and-Go” verification style, as Xilinx director of software product marketing Hitesh Patel terms it, has become counterproductive. The odds of creating a multimillion-gate design so close to perfection that you could debug it from the pins on the package are vanishingly small. So, design teams have begun to employ software-based simulation of the design, much as ASIC teams have done for years.
The huge advantage of simulation, of course, is access. You can observe any signal in an RTL design down to clock-cycle resolution. You can control the state of the design to whatever degree you find worthwhile. Observability and controllability are limited only by your knowledge of the RTL and your skill with the simulation environment. You can work interactively on limited areas of a design, or you can set up grand experiments that may run for days. And the relatively speedy setup of simulation runs makes it possible to try lots of things quickly.
| Link to the complete version of this story on EDN . |
But simulation also raises a series of important questions: Should the role of simulation in an FPGA design be the same as it is in an ASIC design? Should the verification team still, at some point, just put the design in the target FPGA and start testing it at-speed? If so, when is that point?
To find out what design teams are doing today, I spoke with some of the people who work most closely with FPGA users. And for reference, I asked a few ASIC design teams who use FPGA prototypes in their verification processes for their views as well. The full online version of this article, which appeared in the February 19 issue of sibling publication EDN, explores the answers they gave, suggesting that large-FPGA designs can benefit from an ASIC-like design flow, despite the lack of established guidelines for blending simulation. Link to the complete article on EDN.
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