Going beyond design for test
An exclusive interview with a technical leader
By Larry Maloney, Contributing Editor -- Test & Measurement World, 5/1/2009 2:00:00 AM
 JOSEPH SAWICKI VP and General Manager Design-to-Silicon Division Mentor Graphics Wilsonville, OR An expert in finding solutions to IC nanometer design and manufacturing challenges, Joseph Sawicki is responsible for Mentor Graphics’ design-to-silicon products, including the Olympus-SoC place-and-route system, the Calibre physical-verification and design-for-manufacturing platform, and the company’s silicon test and yield analysis product line. Sawicki joined Mentor Graphics in 1990 and held previous positions in applications engineering, sales, marketing, and management. He earned a BSEE from the University of Rochester and an MBA from Northeastern University’s High Technology Program. Contributing editor Larry Maloney interviewed Sawicki by phone on the latest test technologies for preventing failure and boosting productivity in IC design and manufacturing. Read a continuation of this interview. |
Q: How important is DFT (design for test) in IC design?
A: DFT is really the fundamental driver of the economics affecting the IC design chain. It’s the primary method of eliminating defective parts. If you do a poor job of test planning or if you introduce ineffective tests, you risk damaging product quality and your company’s reputation. Test costs also have a direct impact on the cost of goods sold, which is why it’s essential to prevent inefficiencies in manufacturing tests that cause false rejections and reduce yield. There’s a major trend toward leveraging test and diagnostic information over a product’s life cycle to improve yield and company profitability.
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Joseph Sawicki discusses the latest test technologies for preventing failure and boosting productivity in IC design and manufacturing in the continuation of this interview. |
Q: What factors are making IC test more challenging?
A: Obviously, as you increase functionality on a chip, you add to the number of test vectors needed to verify that functionality. So, we see growth in test data volume caused by growing gate counts, as well as new tests required to detect subtle defects as IC feature sizes shrink. In addition, because of high-speed serial buses and packaging limitations, there’s been a reduction in the number of digital pins available for test.
Q: What are some of the new failure mechanisms that crop up?
A: Engineers encounter subtle timing-related and parametric types of defects, such as resistive shorts and opens, resistive vias, crosstalk, and other noise-related issues. As a result, at-speed scan testing has become a crucial part of test suites. This can increase test data volume by up to five times, which is driving adoption of embedded compression. By reducing the size of test patterns that need to be fed externally from the tester, compression ensures that test data can fit on the available test equipment, and it helps minimize test duration and costs. It’s important to choose a test methodology and compression technology that can generate test patterns to detect hard defects and subtle issues as well.
Q: Whose responsibility is it to perform DFT?
A: The trend is to move silicon test away from the designer toward engineers who understand test, device failure mechanisms, and the impact of test strategies on manufacturing costs. With aggressive design requirements and schedules, designers are less willing to make design changes specifically for test. They rely on test engineers to implement systems and software that carry out test requirements without impacting design architectures. This puts more pressure on test engineers to maintain high test quality with minimal test access, while keeping costs manageable.
Q: What are Mentor’s prime DFT products?
A: FastScan is our original test pattern generation tool, but many customers have adopted our newer TestKompress tool, which features high test pattern compression to manage growing test data volume. TestKompress provides the same test patterns as FastScan, but it also compresses the volume of test data and test application time in manufacturing by as much as 100 times.
Q: What role does your YieldAssist tool play in DFT?
A: YieldAssist analyzes test failure data and identifies systematic defect mechanisms that affect yield. This tool works directly with production test failure data from test patterns generated by TestKompress, FastScan, or MBISTArchitect. Instead of using test data only as a pass/fail defect-screening mechanism, this tool helps you to understand the cause of failures and to identify defects that affect yield. As a result, it is becoming a vital tool to help customers ramp up yield and reach their DPPM (defective parts per million) goals.
Read the continuation of this interview.
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