Make way for PCI Express
A serial communications bus will likely replace the parallel bus on all PCs.
Martin Rowe, Senior Technical Editor -- Test & Measurement World, 10/1/2003 2:00:00 AM
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The PCI bus that lets you add peripherals such as modems, sound cards, digitizers, and IEEE 488 interfaces to computers is showing its age. Within two years, PCI Express, a high-speed serial bus, will likely replace the existing 32-bit-wide PCI bus on new servers and desktop computers (Ref. 1).
Intel and IBM are developing ICs that will bring PCI Express to servers and then to desktop PCs. Companies such as PLX Technology are developing bridge ICs and switches for the serial data bus. (See "What is PCI Express?" p. 36, for a discussion of the bus architecture.)
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PLX Technology engineers Gary Wallichs (standing) and Anoop Parambath use a PCI Express emulation PCI Express brings new signals and measurement challenges to the table. If you're familiar with serial buses such as USB, IEEE 1394, or Fibre Channel, then some of the measurements will be familiar to you. |
The most striking difference between PCI Express signals and those of parallel buses occurs when a bit's logic level changes. PCI Express uses pre-emphasis (sometimes called de-emphasis) to distinguish between transition bits (0 to 1 or 1 to 0) and non-transition bits (0 to 0 or 1 to 1).
Mike Engbretson, product manager for high-performance oscilloscopes at Tektronix, says that the PCI Express spec requires that a bus transmitter send transition bits with amplitudes between 3 dB and 4 dB higher or lower than non-transition bits (Figure 1). You'll see this difference more easily at the transmitter end of a PCB trace, because losses in transmission will reduce the differences at the receiver.
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Figure 1. PCI Express signals differ from those of other serial buses because each logic level has two possible amplitudes. |
Imagine a series of transition and non-transition bits overlaid to form an eye diagram on an oscilloscope. Because of the preemphasis in the transition bits, you'll see four distinct amplitudes, two for each logic level, 3.5 dB apart (Figure 2a). Thus, you need to perform two mask tests to verify signal integrity (Figure 2b).
To build an eye diagram, an oscilloscope must sample many bits and overlay them. It must also recover a data stream's embedded clock. Unlike those of some other serial buses, a PCI Express receiver may use a phase-locked loop, phase interpolation, or oversampling to recover the clock from the data. To allow for different recovery techniques, the test specification calls for clock recovery from 3500 bits, or unit intervals (UIs).
From those 3500 UIs, an oscilloscope builds an eye diagram and makes compliance measurements from the center 250 bits. "Unfortunately, 250 isn't a very good statistical sample" says Engbretson. "To reduce uncertainty, you should accumulate measurement results over many 250-bit acquisitions."
To perform an eye test on a PCI Express signal, you need to generate a data stream. You can use a pattern generator or a PCI Express bus exerciser/analyzer. A bus exerciser can generate pseudorandom bit sequences for making eye measurements, and it can generate and analyze data packets that comply with the PCI Express specification.
PCI Express bus exercisers use a bus extender card that contains transmitters and receivers. The transmitters and receivers prevent the extender card from distorting the bus signals because they maintain the same distance from the microprocessor's I/O chipset that you'd get when installing an I/O card into the PCI Express connector.
The distance that a PCI Express signal must travel and the travel path affect its integrity. PCI Express signals use differential signaling, so the PCB traces that constitute a PCI Express lane must be identical because the losses caused by vias, test pads, and connectors must be equal. Furthermore, the total loss can't exceed 13.2 dB.
When you measure the eye of a PCI Express data stream, make the measurements as close to the transmitter or to the receiver as possible; losses and reflections in PCB traces will invalidate your measurements if you make them elsewhere.
Nader Saleh, president of Catalyst Enterprises, says that for embedded systems, you need test pads, called midbus pads, to connect oscilloscope, logic analyzer, and bus-analyzer probes. Those pads should reside on engineering prototype boards only; they shouldn't appear on production motherboards or I/O cards because the stubs formed by the pads will degrade signals.
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Figure 2. a) Overlaying PCI Express bits produces an eye diagram with two amplitudes per logic level. b) PCI Express signals require different eye masaks for transition bits (left) and nontransition bits (right). Courtesy of Tektronix. |
"Know your probe's characteristics," warns Saleh, "because your probes can affect signal integrity." Make sure the oscilloscope and logic analyzer probes don't add too much capacitance to the transmission line. A PCI Express lane can tolerate no more than a few picofarads; a greater capacitance will introduce an impedance discontinuity that will affect the waveform.
To test how PCB traces affect signals, you can use a time-domain reflectometer (TDR) oscilloscope and software. Important measurements include insertion loss, return loss, and crosstalk. Dima Smolyansky, marketing manager at TDA Systems, notes that insertion loss is typically around –10 dB. Return loss and crosstalk measurements should approach –25 dB.
Fixture comes first
Engineers at IBM and PLX Technology are designing ICs that incorporate PCI Express for use on motherboards and I/O cards. IBM's server group in Raleigh, NC, is developing a core chipset that will handle all memory and I/O operations for Intel processors. PLX Technology is developing chips that will bridge different I/O buses to PCI Express devices and switch chips that will allow the devices to communicate with each other.
When testing early designs of devices containing PCI Express, each company starts with a test fixture that provides access for instrument probes to transmitter and receiver pins where engineers can connect oscilloscopes, logic analyzers, and bus analyzers. The test fixtures include test pads, but production motherboards and I/O cards won't. Test pads located between the transmitter and receiver let engineers connect logic analyzers and PCI Express protocol analyzers that monitor bus traffic.
Self-test functions
Core chipsets and bridges sometimes contain built-in self-test (BIST) functions such as a random bit generator from which engineers can verify signal integrity. "These tests don't provide real-world situations," says Tom Bradicich, CTO for X-Series servers at IBM, "but they do give us confidence that the devices will work when we run them under an operating system." After IBM's devices pass initial tests, engineers install them into prototype server motherboards that run Linux.
Jack Regula, chief technology officer at PLX Technology, notes that his engineers had to develop their own test tools because PCI Express is so new. For example, PLX engineers emulated their bridge and switch logic in field-programmable gate arrays (FPGAs) using serializer-deserializer (Serdes) test chips. They built logic-analysis functions into the FPGAs and developed protocol analysis software, too. "We prefer to buy testers, but we develop our own when none is available," he notes.
Bradicich says that IBM engineers have had to develop their own probes for connecting test equipment to chip I/O signals because of the tight mechanical requirements. But he adds that test equipment has kept up with the speed and bandwidths requirements of serial data buses.
Development of PCI Express products will accelerate once motherboards with the bus appear on the market. In the meantime, test equipment will likely keep up with developments because many equipment makers send representatives to the technical committee within the PCI Special Interest Group (www.pcisig.com) that is responsible for developing the PCI Express specifications.
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What is PCI Express?
PCI Express is poised to replace the PCI bus (a parallel bus) with a serial data stream. Instead of addressing I/O peripherals with parallel address and data lines, PCI Express sends data packets along a serial connection. Therefore, it's a point-to-point bus much like Fibre Channel, USB, IEEE 1394, and Ethernet.
PCI Express is a chip-to-chip data bus that lets microprocessors communicate with external buses, such as USB, or with internal I/O cards. It uses 1 to 32 data "lanes" to send the information. Each lane consists of two 2.5-Gbits/s transmitters and two receivers, one for each direction of data travel between the host and the peripheral. The bus may contain 1, 2, 4, 8, 16, or 32 lanes to accommodate higher bandwidths. Each data lane uses the common 8B/10B encoding scheme, which forces enough transitions in the data stream for a receiver to extract an embedded clock.
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A PCI Express lane consists of two transmitter/ receiver pairs. |
Core chipsets, consisting of a memory bridge and an I/O bridge, communicate with the CPU (figure). A switch will communicate between the I/O bridge and all PCI Express peripherals. Over time, this model may evolve so that PCI Express is the only I/O bus that communicates with the core chipset. All other buses such as USB and IEEE 1394 will require conversion to PCI Express. Initially, the parallel PCI bus will coexist with PCI Express on desktop PCs and servers. PCI Express will also replace today's Advanced Graphics Port, used with graphics cards.
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