ATE firm responds to RF chipmaker’s call
Rick Nelson, Chief Editor -- Test & Measurement World, 8/7/2007 1:32:00 PM
"We generate ideas, and those ideas eventually get made into silicon," said Octavio Martinez, director of test engineering at Qualcomm, during a session titled “Critical Issues in Test” at Semicon West, as I reported last month. But, Martinez said, the CDMA chipmaker is looking to ATE vendors to help address the challenges of testing cell-phone chips containing DSPs, graphics processors, 1-GHz microprocessors, memory, and as many as 12 radios.
One test vendor who responded to Martinez during the “Critical Issues in Test” session was Gary Fleeman, director of business development at Advantest America, who described a gamut of innovations ranging from design-automation software to materials-handling equipment. As for software, he said, firms are offering tools that support redundancy (for the internal repair of stuff that doesn’t work), built-in self test (for on-chip test generation), design for test (to reduce test hardware requirements), and diagnostics (to support yield learning).
Focusing on the test-equipment side, Fleeman described what he called a “honeymoon package—an arranged marriage of efficiency” between test resources and handling equipment. That marriage, he said, enables high-throughput, cost-effective test solutions that can provide multisite test of stacked-die devices that combine high-speed digital circuitry, multicore processors, embedded flash and RAM, and multiple RF cores. Seamless integration of the test handler is critical, he said, because of the detrimental effects handler jam rates can have on throughput in systems that aren’t seamlessly integrated. He presented a chart showing that a jam rate of just 1/2000 can reduce throughput from an ideal 30,000 UPH down to significantly less than 20,000 UPH.
On the Semicon West exhibit floor, Advantest demonstrated a T2000 LS mainframe linked to a M4841 dynamic test handler in an integrated SOC test cell. The OpenStar-compliant cell supports parallel testing of 16 high-pin-count BGA, CSP, QFP, and other consumer devices with throughput up to 18,500 UPH—a threefold improvement over its predecessor. It employs Advantest’s Soft Touch handling using electro-pneumatic air pressure to avoid damaging miniaturized parts during touchdowns.
Fleeman concluded his “Critical Issues in Test” presentation by saying that seamless integration and parallelism coupled with streamlined software and development will lead to dramatic per-site test cost reductions. That’s in keeping with the conclusion of Qualcomm’s Martinez, who emphasized that for him the bottom line is cost. Traditionally, he said, ATE capital expenditures have not been falling in concert with chipset average selling prices, adding, "ATE makers must keep up with relentless pressure to reduce cost of test."
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