Test Ideas: Emulate SPI signals with a digital I/O card
Four I/O lines let you test microcontroller-based products.
By Andy Street, Autoliv Electronics, Lowell, MA -- Test & Measurement World, 6/1/2009 2:00:00 AM
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When developing a design-verification tester for millimeter-wave SOC (system-on-chip) devices, my co-workers and I needed to combine switching, electrical measurements, temperature measurement, a parallel digital interface, and a serial digital interface into one instrument. To minimize rack space, we used an Agilent Technologies 34980A multifunction mainframe, which we were already using for DC switching and temperature measurements. By adding an Agilent 34950A 64-bit digital I/O card, we developed a digital interface that emulates both an SPI (serial peripheral interface) bus and a simple parallel bus.
The 34950A groups its I/O lines into two banks of four 8-bit channels. It provides 64 kbytes of memory per bank for pattern generation or signal capture. It also has three I/O lines per bank for handshaking. We found, however, that the card’s handshake lines provided insufficient control for implementing SPI transactions. To get the proper control, we emulated the SPI bus using three of the I/O lines.
SPI is a master-slave protocol originally used with Motorola microcontrollers. Today, it’s become the control interface in a variety of ICs including PLLs (phase-locked loops) and RF ASICs (Refs. 1, 2). The SPI bus is based on four lines:
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CLK. The clock signal from master to slave. All SPI signals are synchronous with this clock;
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SS. The slave-select line (selects the slave for communication);
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MOSI. The master-out, slave-in data line; and
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MISO. The master-in, slave-out data line (not used in some implementations such as PLL control).
The SPI bus uses one of four possible operating modes that specifies the clock edge used for toggling and sampling and the clock idle level. There is no requirement on voltage levels or data rates, and many SPI implementations can use clock rates greater than 10 MHz.
Figure 1 shows a block and timing diagram of the 34950A bank 1, when configured for synchronous, buffered output where H0 through H2 denote the handshake lines. An illustrative SPI transaction is also shown for reference.
 Figure 1. The 34950A synchronous buffered output uses the falling edge, making it unsuited to rising edge SPI implementations. |
You cannot use the 34950A’s handshake lines to emulate all modes of the SPI bus because the bus latches data on the falling edge of the clock, making the bus unsuitable for slaves that use the rising edge. Inverting the clock polarity is not a solution because the last data bit may be lost. Furthermore, if you write a number of transactions to a slave, you must store each transaction as a separate trace memory in the 34950A.
While each bank can support up to 64k x 8 bits, the number of traces that can be stored is limited to 32. That limits the number of SPI transactions. In addition, the card lacks a sequencer, so you cannot download a number of bit patterns and then play them in sequence. You must load each pattern into the I/O card’s memory, and then play each pattern under SCPI control from a host computer. That makes multiple transactions slow.
Instead of using the handshake lines, we use three of the data lines to emulate the SPI bus. The software driver for the card has to translate the data into an SPI bit stream. The algorithm, expressed in pseudocode below, translates a hexadecimal string, DH, of characters to an SPI signal. LD, LSS, and LCLK are integers to define which data outputs represent the MOSI, CLK, and SS, respectively.
n1 = string length of DH
n2 = 8 • n1 (# of samples in payload: 4 bits per Hex character, two times over-sampling to phase clock)
DB = binary array representing DH (array size is 4 • n1)
DB2 = oversample DB by a factor of two (array size n2)
SS = array of 0’s of size n2
CLK = array of alternating 1’s and 0’s of size n2
Payload DS = DB2 × 2LD + SS × 2LSS + CLK × 2LCLK
Set prefix/postfix for SS: PRE = (array of 1’s length NPRE) × 2LSS and POST = (array of 1’s length NPRE) × 2LSS
Concatenate the arrays PRE, DS, and POST to form SPI signal
 Figure 2. An MSO screen shows the SPI transactions using the digital I/O lines. |
Assuming a 24-bit register write with two bits of overhead for the SS prefix and postfix, the 64-kbyte memory could support more than 1000 SPI transactions. The above approach has two additional advantages: The three lines that form the SPI bus are under software control, which provides cabling flexibility, and the implementation can support multiple slaves through the use of additional SS lines.
Figure 2 shows an MSO (mixed-signal oscilloscope) screen that shows the SPI transaction (~CS denotes SS). The SPI clock rate is 5 MHz, which is limited by the internal 10-MHz clock of the 34950A. The different payload sizes correspond to writing data to 16-bit and 24-bit registers within the slave.
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