Synopsys enhances Star-RCXT and PrimeTime
-- Test & Measurement World, 7/29/2006 4:44:00 PM
In addition to debuting PrimeYield at DAC, Synopsys also announced enhancements to its Star-RCXT extraction tool and the Synopsys PrimeTime static timing-analysis tool. PrimeTime VX and Star-RCXT VX add statistical analysis capabilities to allow customers to reduce margins, improve design robustness, and enhance parametric yield.
"Synopsys is in a unique position to address the uncertainties of sub-65nm design by providing a comprehensive variation-aware design solution that closes the loop with silicon," said Antun Domic, senior VP and general manager of Synopsys' implementation group. "The breadth of our solution is a result of linking our investments in a number of strategic areas, including test chip technology, process modeling (TCAD), sign-off, and physical implementation, as well as CCS-based [Composite Current Source] statistical library and sensitivity-based parasitic file formats to address emerging design challenges. At the heart of this solution is statistical analysis and extraction technology built on industry standards, which together help to ensure proven accuracy, design flow correlation, and improved productivity."
"TSMC has been working with Synopsys on variation-aware design," said Wan at TSMC. "We have tested the accuracy of Synopsys' statistical analysis solution and are encouraged by the results."
"The PrimeTime static timing analysis and Star-RCXT extraction solutions have long been the standard for sign-off in our design flow," said Philippe Magarshack, group VP and general manager, Central CAD and Design Solutions, at STMicroelectronics. "We are pleased with the seamless integration of statistical analysis on this important foundation, enabling the adoption of this emerging technology, that is very much needed for 65-nm and 45-nm complex SOC designs."
"Our member companies rely on STARC to drive the next level of design productivity required for each successive technology node," said Nobuyuki Nishiguchi, a VP of development at the Semiconductor Technology Academic Research. "A variation-aware design flow is a key component of meeting this goal for 65- and 45-nanometer designs. Synopsys' variation-aware solution delivers the comprehensiveness required to address emerging challenges due to design uncertainties at these small geometries."
STARC, http://www.starc.jp
STMicroelectronics, http://www.st.com
Synopsys, http://synopsys.com
TSMC, http://www.tsmc.com
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