Parallel IEEE 1149.1 technique optimizes PCB test and configuration
C.J. Clark, Intellitech, and Mike Ricchetti, ATI Research -- Test & Measurement World, 6/1/2004 2:00:00 AM
| Download the PDF of the paper "New Strategies for Cost-Effective Production PCB Test and Configuration" |
Test and configuration times for PCBs continue to rise despite the need for production cycle times (or 'beat rate') to decrease to handle greater production volumes. Manufacturers thus seek new approaches that can keep up with the line rates despite the increasing complexity and nonvolatile memory content of today's PCBs and systems.
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To cut costs, you can replace a traditional PCB test line (top) with one based on a parallel 1149.1-based approach (bottom). |
The traditional in-circuit test (ICT)-focused flow begins with off-board or in-line flash programming to achieve reasonable throughput. That step is followed by automatic x-ray inspection (AXI), automatic optical inspection (AOI), ICT with a bed-of-nails fixture, and functional test. To save test steps, engineers have loaded onto ICT analog tests, discrete digital device tests, boundary-scan tests, and boundary-scan in-system programming. However, the total time of these tasks may not exceed the production cycle time.
A better approach reduces ICT complexity—requiring minimal Pogo pins—so a manufacturing defects analyzer or legacy ICT system could suffice for applying analog and static digital tests. This flow eliminates the initial flash-programming step, combining programming and configuration tasks with boundary-scan digital tests in a parallel IEEE 1149.1-compliant test stage.
This new flow can afford significant cost savings while maintaining high production beat rates. For a system in which Intellitech's PT100 serves as the parallel 1149.1 test and programming stage, the total test line cost (including inspection and electrical test systems) can shrink from $1.046 million to $695,000 for testing (at one board every 30 s) high-volume PCBs each containing one Intel 28F640W30 and two Xilinx XC95288XV CPLDs.
To see the details of this and other cost analyses and to learn the details of how to set up such a test flow, see our complete paper at www.tmworld.com/boundaryscan.
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