Scan basics
A companion article to "Launch-off-shift at-speed test," which appeared in our June 2007 issue.
By Noam Benayahu and Arik Chechik, Metalink, and Ron Press, Mentor Graphics -- Test & Measurement World, 6/1/2007 1:59:00 AM
| Return to "Launch-off-shift at-speed test." |
Scan technology enables high levels of defect detection using automated tools. Each D flip-flop (DFF) or latch in the circuit under test is implemented as an equivalent sequential element called a scan cell that includes extra test features.
During scan mode, scan cells become concatenated into several long shift registers called scan chains. Thus, all sequential gates can be serially loaded for control and serially unloaded to observe. As a result, automatic test-program generation (ATPG) tools can create patterns, since the complex nature of the circuit is separated into the small combinational logic between scan cells.
At one time, scan testing was predominantly static, using patterns called stuck-at patterns. Stuck-at patterns target faults that act as if a gate terminal is stuck at either a logic 1 or logic 0. Clocks operate at frequencies much slower than normal device operating speeds during static tests. With the introduction of 130-nm and smaller fabrication processes, however, the population of timing-related defects grew to the point that static testing was not sufficient (Ref. 1).
Functional test was previously used when patterns were necessary to check for at-speed operation. But generating functional at-speed test patterns is a difficult and expensive task. Even if enough time and circuit knowledge exists to generate patterns, it is extremely challenging to produce a functional pattern set with high coverage. Consequently, scan test has been adapted to detect timing-related defects. Similar to standard static scan tests, high coverage at-speed scan testing can be automatically produced with ATPG tools
REFERENCE
1. Benware, B.R., et al., “Effectiveness Comparisons of Outlier Screening Methods for Frequency Dependent Defects on Complex ASICs,” Proceedings of the 21st IEEE VLSI Test Symposium (VTS 03), IEEE Computer Society Press.
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