EEPROMs store calibration data
The use of EEPROM to allow products to be calibrated when tested has introduced a whole new set of test-program rules.
CH Lim, National Semiconductor -- Test & Measurement World, 9/1/2003 2:00:00 AM
In the past, many analog products underwent zener and link trimming operations at the device sort stage to tighten the distribution of selected parameters, such as output voltage. The trimming process occurred at wafer level, making use of additional pads designed pecifically for that purpose. Once a die was trimmed to a certain target, the parameter was locked, with reversal almost impossible.
A more flexible approach allows multiple trim operations at the wafer or package level. This approach employs EEPROM cells to store calibration data. The introduction of mixed-signal products in MOS processes allows the use of EEPROM for this purpose. For National Semiconductor, such EEPROM was first introduced in the company’s CS100 process, and EEPROM later appeared in the CS65 process as well. One of the first devices that benefited from EEPROM calibration was the LM78 system health monitor, which was designed to CS100 process. Other products that subsequently followed the trend were digital temperature sensors like LM70, LM74 and LM77, which were designed in CS65 process.
The introduction of EEPROM programming at the final-test level has necessitated the introduction of a new set of programming rules to check the die condition and quality at different programming stages. The end result of such rules is to ensure that the final product is accurately programmed to the required target without introducing a non-standard test process.
EEPROM checks
Since EEPROM’s are memory cells, testing this class of devices requires validation beyond just normal parametric and functional testing. One of the tests that have been specifically designed to check the integrity of the EEPROM memory is known as the data-retention test (DRT).
The primary reason for the DRT is to screen out any die with bad EEPROM cells that would make a die impossible to program, be incorrectly programmed, or to have the potential to lose the programmed data. In the last case, data loss could occur due to charge leakage of the memory cell over time or when excited by stress conditions in application. High temperature and abnormal stress voltages are known to induce charge losses that could lead to device failure. Therefore, the test operation needs to be able to weed out such bad EEPROM cells.
In the first generation of EEPROM devices, the design was aimed at replacing the use of zeners and links to "calibrate" a desired parameter to its target. Not much attention was paid to the testability of the EEPROM cells themselves. As a result, first generation devices usually do not allow direct testing of the EEPROM bits. In order to screen out bad EEPROM cells, parametric testing is done and limits are set to screen out any unit that falls apart from the normal distribution for the programmed parameter. Examples of such parameters include the internal clock rate, reference voltage, and temperature. This is done both before and after programming the device in the following manner:
Indirect EEPROM testing
Indirect EEPROM testing involves these steps:
EEPROM cycling. EEPROM cycling can take place at wafer test. All EEPROM bits are read/write cycled alternatively between ones and zeros, where each cycle writes and erases the EEPROM cells. The purpose for cycling the EEPROM is to ensure that they could be programmed and erased. Empirical studies show that when cycled, the memory cells’ gate threshold level, VT improves; thus cycling could reduce the risk of data loss caused by voltages beyond operating ranges. The negative impact from this step is an increased in test time, as there is an overhead associated with each cycle. Subsequently, every die is programmed to a known bit value, usually either all zeros or all ones. Parameters affected by the EEPROM programming are read parametrically, and the individual values are checked against a set of limits. Any die falling out of the limits are indirectly implicated for EEPROM failure.
Wafer bake. After wafer-level cycling and checkerboard programming, every wafer needs to be baked at 225°C for 12 hours. Baking the wafers at such high temperature simulates a stimulated stress condition. EEPROM cells with leakage path will likely see charge losses under such stress condition. After bake, wafers are stored at room temperature until they are needed for packaging and final testing.
Final testing. At package level, testing is indirectly done once again on the EEPROM by reading the programming parameters. Assuming that charge loss has occurred to one of the EEPROM bits, it is expected to cause a parametric drift that will lead to its reading failing pre-set limits. There is a certain inaccuracy in this mechanism however. Since the parametric distribution for different dierun could vary (which is one of the reasons why trimming is required), the limits set to reject units with data loss might not be tight enough to reject a unit with a drift that is caused by a bad low-significant bit. If the limits were set too tightly, chances are that a process variation in Fab will cause the distribution to intersect the limits, thus giving poor yields.
Direct EEPROM access
Learning from experience, engineers designed the next generation of EEPROM products to begin to allow EEPROM cells to be accessed directly for test. An example of such an EEPROM-based product is the LM70 digital temperature sensor. This enables a better DRT test sequence that allows precise data retention checking through the following steps:
Checkerboard cycling. Checkerboard cycling at wafer test remains in place. Just as in the indirect-test case, the cycling process improves the gate-threshold level in order to improve data-retention capability.
Program checkerboard pattern. In the last cycle, all EEPROM bits are programmed to a checkerboard pattern that will be used for a bit-wise data-retention check in later steps. For example, a 12-bit device might be programmed to 1010 1010 1010.
Wafer bake. This step is again similar to that which occurs in the indirect-test process. Baking at high temperature aggravates the memory cells and accelerates any data loss due to charge leakage.
Data retention check. When the preprogrammed die are assembled and packaged for final test, the final-test program first determines the data integrity for each unit by reading back the pre-programmed EEPROM data. For a good unit, the data read back will be the same as the checkerboard pattern programmed at wafer level. If any bit fails to match up with the known checkerboard pattern, the unit is flagged for data-retention failure. In this case, a 12-bit device must read 1010 1010 1010 before it could pass the data retention check.
Parametric and functional testing. If a unit passes the data-retention check in step 4, other parameters are checked, and the EEPROM bits corresponding to the "calibrated" parameter are burned into the EEPROM memory for storage. A post-programming sequence checks that the unit meets all datasheet specifications. If a failure occurs, the unit is rejected.
Test scenarios
In the test environment, process standardization is essential on production line so that no special operators intervention is required when testing any class or family of products. The same rule holds true for EEPROM devices. To an operator, the process to test this class of devices should not differ from that of any other products on the line.
One of the ways to standardize the test process from engineering standpoint is to build a set of rules into the test program (see figure). To understand what rules and checks are needed, it is necessary to understand the different test situations when final testing a product:
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| An effective test program should seamlessly handle new and previously tested devices without operator intervention. |
Testing fresh units. Units are tested for the first time after the die have been packaged.
Re-test of rejects. This is a standard process in many manufacturing processes to validate the failures from the first test operation. Devices that were improperly failed can be reclaimed when re-tested.
Re-test of accepted units. Accepted units from a previous test operation are re-tested if a test-system failure is detected.
In all these scenarios, different check conditions are required in the program so that a single program can be used to detect each unit’s EEPROM status. The reason for these checks is to allow the use of a single program to test the device regardless of the scenario in which a unit could have come from.
For fresh units tested for the first time, the test steps outlined for the DRT in an indirect-test process holds. The re-test scenarios introduce their own complications.
Re-test of rejects
When re-testing rejects, one of the problems is that a reject is likely to fail the data-retention check in the program, since this segment of the program expects to read back the checkerboard code programmed at wafer level. When a unit has already been calibrated and the calibration data burned into the EEPROM cell, the EEPROM will no longer hold the original checkerboard pattern.
One of the ways to overcome this problem is to re-test rejects using a different program where data retention is not checked. This method is, however, a risky one, as the program could be incorrectly used to test fresh units, allowing data-retention failures to escape.
A better way is to have a procedure that re-programs the whole set of EEPROM bits to their original checkerboard pattern whenever a unit fails after its EEPROM bits have been overwritten by new calibration data. In so doing, a rejected unit could now be re-tested using the same program. One of the rules for doing this is that the reprogramming should only be done to a rejected device if it already passed a data-retention check earlier. A unit that already failed a data-retention check should be rejected straight out, with no reprogramming allowed. This way, units with bad EEPROM bits will continue to be rejected by the data retention check sequence.
Re-test of accepted units
Another test scenario is the re-test of accepted units. In the course of production testing, tested good units might need to be re-tested. A robust test program should handle this scenario as well, so that a unit that has already been calibrated will not fail a data-retention check. At the same time, the program must be able to differentiate a genuine failure caused by defective EEPROM cells.
To enable accepted units to be re-tested using the same program, an embedded check of one of the trim parameters is needed when checking for data-retention failures. If a unit fails data retention, the program should read back one of the trim parameters (for example, its reference voltage or internal clock rate) and compare the reading against a set of final limits for the affected parameter. If the trim parameter falls within these limits, it can be deduced that the unit has already been tested before and is a good unit. The program can now force the data-retention test to return a "pass" value so the program can continue to move on to the other tests.
For a fresh unit, the embedded check is not performed since the unit will pass the data-retention check. If the unit is a genuine bad unit with EEPROM data-retention problems, it will fail the data-retention check and is expected to also fail any parametric test. In such case, the unit is rejected as a data-retention failure.
Conclusion
The testing of EEPROM products places a new requirement to test-program algorithm so that the same program can be used to test fresh units, to re-test rejects, and also to re-test accepted units. A robust program should be able to screen out genuine EEPROM data-retention failures caused by defects in the EEPROM memory cells without rejecting good units that have already been calibrated. Incorporating embedded parametric checks into the program during data retention test of the EEPROM is a good practice. The design of EEPROM devices should also allow the EEPROM bits to be read back bit-wise to enable the use of program logic to effectively screen out bad units.
Chong Han Lim is a test-engineering manager of National Semiconductor's test facility in Malaysia and is in charge of data conversion, interface, and flat-panel display products. He leads a group of engineers in supporting new product releases and development of test solutions for better test efficiency. He graduated with an honors degree in electrical and electronic engineering from the University of Leicester, United Kingdom. E-mail: chong.han.lim@nsc.com.
Copyright 2003, National Semiconductor.
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