EDA tools address IC cost and yield
Rick Nelson, Chief Editor -- Test & Measurement World, 3/1/2005 2:00:00 AM
To continue developing high-quality ICs in ever-shrinking process geometries, designers must rely on EDA tools that embed detailed knowledge of process characteristics. This move continues a trend I commented on in "EDA gains larger role in test arena" in our Dec. 2004/Jan. 2005 issue. For example, Giga Scale Integration Corp. (Giga Scale IC) has launched an online service, Virage Logic has released its Silicon Aware IP, and startup Aprio has introduced its first design-for-manufacturing (DFM) software suite.
Giga Scale IC's service, ChipEstimate.com, provides designers with free access to the company's InCyte chip-estimation tool, which helps control the cost of ICs at the design creation and specification stage. " 'Design for Cost' is our mantra," says Adam Traidman, president of Giga Scale IC. To that end, InCyte allows users to estimate IC cost as well as yield, die size, power, and leakage to within 5% to 10% accuracy of final silicon, and it lets them investigate architectural and economic tradeoffs across various technology nodes, process variants, and IP options.
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| ChipEstimate.com helps designers estimate IC cost, yield, die size, power, and leakage. Courtesy of Giga Scale IC. |
Virage Logic's goal with its Silicon Aware IP is to provide seamless integration among three classes of IP that might populate a design:
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functional IP, which consists of RTL descriptions of microprocessor and other cores;
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physical IP, which consists of GDS-II representations of memory, logic, I/O, and mixed-signal circuitry; and
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infrastructure IP, which represents BIST, repair, diagnostic, and yield-enhancement functions in either GDS-II or RTL format.
Adam Kablanian,Virage Logic president and CEO, says Silicon Aware IP establishes process-specific testability, predictable quality levels, and fast time to yield, minimizing the test escapes and poor yields that can plague bolted-together physical and infrastructure IP blocks developed independently. Silicon Aware IP lets users make tradeoffs to achieve optimum yields. In an effort to achieve high yields in cutting-edge processes, for example, designers might accept additional chip real-estate overhead, which CTO Yervant Zorian calls "a real-estate investment."
Finally, Aprio Technologies, founded in 2003, is staking its claim as a supplier of what it calls second-generation DFM tools with the release of its Halo suite. The products, says Clive Wu, PhD, Aprio CEO and CTO, are designed to solve the thorny problems that come with chip design re-spins, designs that need optical-proximity-correction (OPC) modification to solve yield issues, or modified designs that require a quick change to mask data. Halo OPC can reconfigure an optical-proximity-corrected layout for a new, optimized OPC result, providing 30 times faster performance in implementing a design change in mask data, according to Wu.
Chip-sized SMD adapter
Ironwood Electronics' new LS-MLF32A-01SMD socket adapter allows users to socket a 32-pin, 0.5-mm pitch micro lead-frame (MLF) chip on a target PCB without requiring any additional PCB area for a socket. The companion SF-MLF32A-01 socket solders directly to the target PCB as would the MLF itself. Pricing for the LS-MLF32A-01 socket adapter begins at $94 each in quantities of 100. www.ironwoodelectronics.com.
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