Test Ideas: DPGA conditions signals with negative time constant
With two op amps and three analog switches, you can build a programmable amplifier that conditions signals prior to digitizing.
By W. Stephen Woodward, Consultant, Chapel Hill, NC -- Test & Measurement World, 9/1/2008 2:00:00 AM
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Digitally programmable gain amplifiers (DPGAs) amplify or attenuate analog signals, which maximizes an analog-to-digital converter’s (ADC’s) dynamic range. Most monolithic DPGAs such as the Maxim LTC6910 and the National Semiconductor LPM8100 use a multiplying digital-to-analog converter (DAC) in an op amp’s feedback loop so that the DAC’s input code sets the amplifier’s closed-loop gain. Instead of using a monolithic DPGA, you can use two op amps and three analog switches to build a DPGA that is based on negative time constants.
You’re no doubt familiar with the e–t/RC convergent exponential in which a capacitor in an RC circuit asymptotically discharges to zero. For input VIN, V = VIN/2 at t = T = loge(2)RC, V = VIN/4 at t = 2T, V = VIN/8 at t = 3T, and so forth.
 Figure 1. A negative time constant causes V to increase exponentially over time. |
Less familiar, but just as simple, is the behavior of the same RC topology when R is replaced with an active circuit that synthesizes a negative resistance (Figure 1). If you replace resistor R with –R, you create a positive RC time constant. Thus, you create a divergent exponential, VINe+t/RC.
Instead of converging to zero, the waveform theoretically diverges to infinity, and V = 2VIN when t = T, V = 4VIN at t = 2T, V = 8VIN at t = 3T, etc. Therefore, you can amplify VIN by simply waiting the right amount of time (t = log2(V/VIN)T) after starting the “negative discharge.” The divergent exponential and the negative time constant are the core concepts of the circuit in Figure 2.
 Figure 2. Positive feedback from amplifier A1 causes C1 to increase in voltage, which amplifies VIN exponentially. |
You can program the amplifier’s gain with a pulse-width modulation (PWM) signal produced from a microcontroller or other circuit. When the PWM signal goes to logic 0, sample-and-hold capacitor C1 charges to VIN. When the PWM signal cycles to logic 1, op amp A1 drives the R1C1 positive-feedback loop, creating a negative time constant.
The resulting divergent exponential rise of C1’s charge continues as long as the PWM signal remains at logic 1. That creates a net voltage gain of VOUT(t) = VIN2(t/10µs + .5). Thus, gain = 2(t/10µs + .5), and log(gain) = 3 + 0.6 dB/µs. At the end of the amplification cycle, when PWM returns to logic 0, amplifier A2 captures and holds the amplified VIN.
The logarithmic relationship between gain and timing provides excellent gain resolution even when a PWM signal has just 8 bits of resolution and its programmable gain has a wide range—better than 0.2 dB/LSB_step. (Click to view 
of gain versus time using the amplify phase.)
The accuracy and repeatability of the timing of the exponential signal, the ADC sampling, the jitter, and the RC time constant stability all limit the amplifier’s gain-programming accuracy. In Figure 2, 1 ns of timing error or jitter produces 0.007% of gain-programming error. Fortunately, the near ubiquity of programmable timer/counter hardware in microcontrollers and data-acquisition systems usually makes it easy to digitally generate a repeatable PWM control signal.
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