On-chip testers gain momentum
Martin Rowe, Senior Technical Editor m.rowe@tmworld.com -- Test & Measurement World, 12/1/2008 2:00:00 AM
|
|
|
With today's communications ICs running serial buses at multigigabit rates, knowing what's going on inside the package is becoming essential. Two IC makers, Vitesse and PLX Technology, have solved the problem by embedding testers into their parts. In both cases, the embedded testers arose from a need for the companies' engineers to debug their devices. Soon, the companies found customers were asking for the testing technology.
Vitesse started several years ago with what is now VScope, which is essentially an equivalent-time-sampling digitizer. Product manager Juan Garza explained that while developing a CDR (clock-data recovery) circuit, engineers needed to view the high-speed signals after they were equalized inside the chip. Conventional test equipment has access to IC pins, but not to the inside of the package. At the time, data rates were 1–2 Gbps. Now, with data rates at 10 Gbps and faster, Vitesse engineers can't live without VScope.
The figure shows how VScope works. It samples a waveform at two points. At the center of the eye, a fixed-position sampler digitizes voltage. At another location—this one can vary across the eye—VScope also samples the signal. From the sampling points, VScope calculates BER (bit error rate). From the difference in BER, PC software can reconstruct the signal eye.
 VScope samples incoming signals with an on-chip digitizer. Courtesy of Vitesse Semiconductor. |
The IC has an SPI (serial peripheral interface) bus from which the device sends the sampled data. A development board converts the SPI signals to USB (universal serial bus) format for transport to a PC. Software then provides a user interface and displays the reconstructed eye diagram. (Click here for more information.)
PLX Technology develops and manufactures switch ICs for PCIe (PCI Express). PCIe is a packet-based protocol, and PLX engineers wanted to decode it to determine when a link was established. Instead of using external test equipment, which consumed bench space, the engineers designed a PCIe packet generator and analyzer into the ICs. “We could figure out what was happening with a logic analyzer,” said principal architect Jeff Dodson, “but we were unable to connect external test equipment to all 24 ports on a switch.”
Dodson has written a paper that explains how the PCIe on-chip exerciser and analyzer works. In a nutshell, the packet generator mimics the ingress stream of TLPs (transaction-layer packets). It can saturate a PCIe Gen2 link in both directions so you can test each lane at full capacity.
The PCIe packet analyzer is independent of the exerciser. It can monitor PCI data streams and keep count of memory reads, memory writes, and completions, all of which are the PCIe bus transactions.
Like VScope, the PCIe generator and analyzer communicates to a host PC through the IC's I2C bus, converted to USB by an evaluation board. PC software provides a user interface where it plots the data. The online version of this article includes a screen image of the PCIe analyzer.
Both companies have found that their customers use the on-chip testers not only when developing products with the ICs, but also when testing deployed systems. In fact, Garza noted that “we have trouble convincing customers to return the evaluation boards.”
No related content found.
- 0 rated items found.
Datasheets.com Electronic Parts & Inventory Search
185 million searchable parts
- Part Number
- Description
- Inventory
- Products
- Manufacturers
View All Webcasts
