Don't Fail Good Boards
By understanding false failures in board testing and the tradeoffs involved in eliminating them, you can improve both the speed and quality of your testing.
Ted T. Turner, Hewlett-Packard, Loveland, CO -- Test & Measurement World, 3/1/1997 2:00:00 AM
(See also the Letter to the Editor received about this article.)
Boundary-scan testing has become indispensable to engineers who need to test digital ICs. Approved by the IEEE in 1990 (see "About Digital Boundary Scan--1149.1," p. 38), the standard has enabled engineers to test components that are too small to probe or ones that don't have direct access for testing. Now, with the explosive growth of complex mixed-signal ICs, engineers need a similar tool for testing interconnects on analog devices.
The solution to this problem seems to be an IEEE draft standard (IEEE P1149.4) for analog boundary scan. IEEE P1149.4 builds on the hardware and software of the original 1149.1 standard and requires newly designed devices to incorporate both digital and analog boundary scan features. The IEEE 1149.4 working group hopes to send the draft standard out for balloting in June (see "IEEE Seeks Input on 1149.1 and P1149.4," below).
Many working-group members believe that analog boundary scan will be practical only if it can test components and networks, both between and inside devices. To meet these goals, the working-group members are using two test chips (see "Test Chips Validate P1149.4 Concepts," below). Looking even further into the future, some device designers want to put all the required test and measurement devices into the product, and they feel that ultimately this can be done at a lower cost than installing an ATE interface connector on the product.
The plan is to have analog boundary scan do everything that digital boundary scan does and more. Digital boundary scan's main function has always been testing for shorts and opens, either inside a device or between devices. Stored or imported digital test patterns help to localize fault locations. Analog boundary scan must also measure component values and circuit parameters such as gain and frequency response.
The working group is defining P1149.4 hardware and software. All devices that incorporate P1149.4 will be compatible, and potential users will know exactly what to expect. But the working group has left the details of measurement techniques to the users, to allow flexibility and promote improvements. So, the user supplies the signal sources and measuring instruments that are best for the job, and P1149.4 provides the hardware switches and software commands to route the test signals and parameter measurements as the user requires. Some developers foresee the complete test and measurement system being situated within the DUT.
Building Blocks of P1149.4
To ensure that device designers will accept and use the 1149.4 standard once it is approved, the working group has kept dedicated pins and additional silicon to a minimum. The 1149.1 standard requires four or five dedicated device pins. So far, P1149.4 requires only two dedicated analog test-bus pins.
The P1149.4 standard builds on the 1149.1 standard's existing hardware and software and must be 100% compatible with it. And, analog circuits on a DUT cannot affect digital boundary scan tests. At the same time, any DUT with the analog boundary scan provisions of P1149.4 has to perform the same interconnect tests as any 1149.1 device, including shorts and opens testing of the dedicated 1149.4 pins and analog pins. An 1149.4 device's test access port (TAP) contains the four 1149.1 control and signal lines, as well as the two additional analog bus lines for 1149.4.
There must also be a "core disconnect" capability to keep analog circuits on the DUT from interfering with digital testing. P1149.4 must provide for disabling or disconnecting analog cores--analog functional blocks in the DUT. Since most DUTs will be mixed-signal devices, they will require 1149.1 testing, and the guidelines mandate this disconnect capability.
The analog pins on the DUT must have boundary scan control cells that are compatible with both 1149.4 and 1149.1 testing requirements. To meet this goal, each analog pin needs an associated digitizer or digital reference whose sole purpose is to make any signal on the analog pin look like a digital 1 or 0 during 1149.1 testing.
Additional capabilities may be added to the 1149.4 standard as options. Just as the 1149.1 standard provides for an optional TAP pin, the 1149.4 standard may include two optional analog test-bus pins. They will allow, for example, differential measurements, but need not be implemented if creating two more dedicated device pins would be unnecessary or impractical. And in spite of the "scan" term used to describe 1149.4, the analog test buses can continuously stimulate and measure the circuit being tested.
The P1149.4 standard defines switches that device designers must incorporate into new devices along with all the other mandated 1149.1 and 1149.4 facilities. Switches isolate components and networks for testing, and they route stimuli and measurement connections to the required locations. These switches are microscopic solid-state devices--as small as 1 m2 (0.0016 in.2)--and their impedance can be 1000 times that of a mechanical switch.
Unlike mechanical switches, these solid-state switches exhibit nonlinear characteristics: Their impedance changes with signal level. If the designer can make a switch larger, then the nonlinearity decreases. Given the lack of available space on most devices, it's often not possible to use a large switch. The 1149.4 working group needs to specify an acceptable range of switch impedance.
An Example of 1149.4 Operation
It's easy to measure an individual component such as a resistor using analog boundary scan, but it's much more difficult to determine component values of even a simple network. Here's an example of how you could make these measurements using analog boundary scan.
Figure 1 shows three interconnected devices with analog boundary scan provisions. Discrete components and networks connect these devices. The 1149.4 test concept works only if you can connect the two analog test buses ABUS1 and ABUS2 to any analog device pin; that explains the multitude of switches in the figure. The working group may set the required number of switches at five per analog pin, with an additional two as options. The source and detector shown can be on the PCB or can be part of an external ATE system. They may ultimately end up inside a chip or an MCM.
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| Figure 1. Switching is at the heart of analog boundary scan. In the analog areas of mixed-signal ICs, switches will allow routing of voltages, grounds, and test buses to the analog core. You will be able to test discrete components and simple networks, both inside and outside mixed-signal devices, by switching stimuli and measuring instruments to the desired locations. Analog device pins will have digitizers (DR) so they will look like digital pins for interconnect tests. (Courtesy of IEEE.) |
To measure the impedance of a resistor in the Z5 location, you would switch in the current source and force a known current through Z5. Next, you would connect the voltage detector across Z5 and measure the voltage drop. You could follow the same procedure to measure the value of a resistor at Z4 even though it is between two devices. In both cases, you would use Ohm's law to calculate the unknown resistance.
Even if Z4 and Z5 were 50 V, and the in-line switch impedances totaled several thousand ohms--a realistic switch impedance--you could measure the resistance of Z4 and Z5 with ±1% accuracy without any special test equipment--a 41/2-digit DMM would be adequate. If you were measuring inductance or capacitance instead of pure resistance, you would need to use a synchronous AC source and detector. The high switch impedances would limit the test frequency, but you could still make a successful measurement. Working-group members are still determining the accuracy limits of such measurements.
Network Measurements Become Complicated
If you could determine the values of components Z1, Z2, and Z3 in Figure 2 using a bed-of-nails fixture and traditional in-circuit test techniques like virtual grounding and multiwire guarding, there would be no problem. But since these components are inaccessible, the traditional methods are unusable. When you use 1149.4 to try to evaluate even simple networks like this one, the entire process becomes extremely complicated, even for simple measurements.
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| Figure 2. To test simple analog networks that you can't probe, you must first measure the voltages developed across the unknown components by currents arriving from two different directions. You can take this data, combine it with data from mathematical simulations of the same network structure with nominal component values, and use matrix algebra to calculate the values of your unknown components. Your test system should perform this procedure automatically. (Courtesy of IEEE.) |
You would start by measuring voltages across the network components Z1, Z2, and Z3 for the two different current flows shown in Figure 3. Next, using a PC and standard circuit-modeling software, you would construct a mathematical model of a circuit with the same topology (structure) as the network you were testing. The component values in your model are not important, as strange as that seems. You would then calculate the voltages and currents in your model. Through a sequence of matrix-algebra calculations, you would end up with the difference between the component values in your model--values that you know--and those in your real network. Addition would give you the answers you need.
Assuming that this technique is the best one to use, you won't have to grind out the results yourself. The test software will include a library of simple network topologies and will do the calculations automatically. All the information needed for performing the test would come from the DUT's CAD file. Even this procedure is not practical for complex networks; fortunately, most networks on mixed-signal devices and PCBs are simple enough to test in this way.
On the software side, the boundary scan description language (BSDL)--which the designer uses to define how boundary scan provisions merge into the DUT's hardware design--needs augmentation in order to support 1149.4. There are two proposed levels of upgrade:
Upgrade BSDL with six new 1149.4 terms to permit full implementation of 1149.4 testing. At present these terms are named
BYPASS, SAMPLE, PROBE, EXTEST, MEASURE, and CLAMP, and the working group is still defining the details of their implementation. These terms may still change, both in name and number.
Keep BSDL the same, but manipulate it so it "fools" 1149.1 software into treating 1149.4 cells as if they were 1149.1 cells. The 1149.1 software can then run tests for "digital" shorts and opens. This is only a partial implementation of analog boundary scan and is not the recommended solution.
Analog Boundary Scan Will Succeed
Even though there isn't an approved standard yet, the future of 1149.4 seems bright. It is firmly based on the proven 1149.1 standard, and the working group wisely decided to define the hardware and software structure but not the measurement techniques. This will leave you free to develop improved test methods to make 1149.4 even more efficient.
Adam Cron of Motorola (Schaumberg, IL), chairman of the 1149.4 working group, says that a long-term goal will be the merger of the P1149.4 standard with the 1149.1 digital boundary scan standard. Considering how strongly 1149.4 already depends on 1149.1, such a move might seem academic, but integration of these two standards would ensure total compatibility and simplify future changes. T&MW
FOR FURTHER READING
"1149.1-1990 IEEE Standard Test Access Port and Boundary-Scan Architecture," IEEE, Piscataway, NJ.
IEEE has a Web site for 1149.4: http://grouper.ieee.org/groups/1149/4/. It contains meeting minutes and other data.
Parker, K., J. McDermid, and S. Oresjo, "Structure and Metrology for an Analog Testability Bus," Proceedings of the 1993 International Test Conference, IEEE, Piscataway, NJ.
The Proceedings of the International Test Conferences held since 1993 contain informative papers on different aspects of analog boundary scan. IEEE, Piscataway, NJ.
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About Digital Boundary Scan--1149.1 About 10 years ago, the density of digital IC circuitry began to cause testing problems: There were too few device pins to let manufacturers verify interconnects on a chip. Concerned electronics manufacturers formed a group that became know as the Joint Test Action Group (JTAG), and after several years, the group produced the four-wire serial test bus known generically as boundary scan. In 1990, boundary scan became IEEE standard 1149.1. With boundary scan, each I/O pin of an IC has an associated shift register. During testing, data is clocked in and out through this serial chain of shift registers. A test access port (TAP) connects the four boundary scan lines--data in, data out, clock, and mode select--and the TAP controller inside an IC runs the test sequence. An optional fifth TAP line transmits an asynchronous reset signal to the ICs if testing requires it.--Joel M. Goldberg Test Chips Validate P1149.4 Concepts To validate the concept of analog boundary scan testing, the P1149.4 working group asked for volunteers to design and construct test chips. In the end, two teams developed test chips. For one chip, Keith Lofstrom Integrated Circuits (KLIC) (Beaverton, OR) designed the IC, and Steve Dolens of International Microelectronic Products (IMP) (San Jose, CA) undertook its fabrication. Another team, consisting of the Hewlett-Packard Manufacturing Test Division (Loveland, CO) and Matsushita Electric Industrial Co. Ltd. of Japan, developed the test chip in Figure 1. According to Keith Lofstrom of KLIC, the two teams had to produce designs that would be compatible with the proposed standard, but because each team had a slightly different goal, the two chips differ. The HP/MEI test chip provides tools to validate 1149.4's ability to test and measure interconnects and components between devices. The chip itself contains solid-state switches--some with impedances externally adjustable from 100 V to 6000 V--and their controller. The test board containing the chip has provisions for mounting discrete components and networks for testing. The KLIC/IMP chip explores the limits of 1149.4 hardware design, especially in the areas of core disconnect switching and test bandwidth. It contains a 50-MHz differential amplifier to help evaluate different switching and bandwidth-related options. --Joel M. Goldberg Copyright 1997, Test & Measurement World. Published by Cahners Business Information, Newton, MA |
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Letter to the Editor (published June 1997, p. 10) Analog Boundary Scan Clarified Overall, I felt that the analog boundary scan article was a service to the test and measurement community and to the P1149.4 draft standard. But I do have a few comments that may clarify the concepts further. I expect that P1149.4 will be used to measure gain and frequency response only in limited situations where conditions are favorable. It will be most helpful in "proof by construction" tests: If a circuit contains all good components and is assembled correctly--as verified by P1149.4 testing--we can eliminate functional verification. This test philosophy works very well for other types of products (like matches, hand grenades, and flash bulbs). Use of the term "DUT" was confusing. Is it an IC, a "device," or a PCB? For P1149.4 purposes, the PCB is the DUT, and it contains discrete components and ICs, some of which may have analog or digital boundary scan provisions. I believe that a square micron is more like 10-9 in. than the 10-3 in. you mentioned; that incredibly small size for a switch is one of the major factors that makes P1149.4 feasible. At the same time the 10-3 - 10-4 ohm on-resistance of these switches (compared to the 10-2 ohm on-resistance of a good reed relay) has a fantastic impact on how we must make measurements. The BYPASS, SAMPLE, EXTEST, and CLAMP terms are already part of the Boundary Scan Description Language (BSDL). A BSDL upgraded for P1149.4 must be able to identify analog pins and the resource devoted to them. Today's BSDL and P1149.1 standard have no concept for an analog pin. Thanks again for bringing the analog boundary scan concept to the attention of the general test and measurement community. Ken Parker Member, 1149.4 Working Group Hewlett-Packard Co. Loveland, CO |
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