Mentor Graphics acquires LogicVision
The move unites BIST, ATPG, and test pattern compression technologies.
-- Test & Measurement World, 8/19/2009 8:07:00 AM
Mentor Graphics and LogicVision have announced that LogicVision stockholders have voted to approve, and the parties have closed, the
. Former LogicVision stockholders will receive 0.2006 share of Mentor Graphics common stock in exchange for each share of LogicVision common stock.
LogicVision is a provider of built-in-self-test (BIST) technologies for testing system-on-chip (SoC) designs. The combination of Mentor’s automated test pattern generation (ATPG) and embedded test-pattern compression technology with LogicVision’s BIST products enables Mentor to provide customers with comprehensive and integrated solutions to address the growing complexity of silicon test.
“Our customers are facing significant new test challenges as they move to each new technology node,” said Walden C. Rhines, chairman and CEO, Mentor Graphics. “We believe the combination of the Mentor and LogicVision silicon-test solutions will enable them to address all aspects of their full-chip test requirements with a unified test platform. Combining our industry-leading ATPG and embedded compression with the LogicVision memory and logic BIST technologies enables our customers to maintain high product quality and test standards, while reducing manufacturing costs and improving profitability.”
“The partnership we started over two years ago that integrated the Mentor TestKompress ATPG and compression tool with the LogicVision ScanBurst at-speed scan technology paved the way for a successful merger of the organizations,” said James Healy, former president and CEO of LogicVision. “We now intend to build on that cooperation to address the critical challenges of silicon test, such as cost-effective nanometer SOC testing, extreme pattern compression, advanced at-speed testing, embedded memory test and repair, high-speed I/O testing, and leveraging test data for rapid yield analysis.”
The combined silicon test solutions from Mentor Graphics and LogicVision provide customers with technologies to address the test challenges of the digital logic and memory portions of their designs, as well as the increasingly common high-speed Serdes analog and DDR-based interfaces. LogicVision’s test bring-up and silicon characterization tools—combined with Mentor’s leading failure diagnosis capabilities—will also help customers accelerate yield ramps, reducing time-to-volume.
LogicVision resources will be fully integrated into the Silicon Test Solutions group within the Mentor Design-to-Silicon division led by VP and GM Joseph Sawicki. The division also includes the Olympus-SOC place-and-route, and the Calibre physical verification, design for manufacturing and resolution enhancement technology product groups.
www.mentor.com
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