Test Ideas: Pulse generator aids IC testing
You can build a circuit that generates up to three pulses for programming an IC's pin.
By Kevin Frick, Maxim Integrated Products, Sunnyvale, CA -- Test & Measurement World, 9/1/2009 2:00:00 AM
|
Have a test idea you'd like to share? Publish it here and receive $150. Send us your ideas. Also: Read other Test Ideas Read Design Ideas published by EDN |
As ICs increase in complexity and decrease in size, their pin counts drop or, at best, remain constant. The result: a need for pin-saving measures like serial programming. In the past, multiple pins might have been available for programming an IC’s current or voltage limit, but today’s ICs often encode that limit as a set number of pulses on a serial line.
You can generate pulses that program an IC’s pin, but you usually need a microcontroller or arbitrary waveform generator. The circuit in Figure 1 can help when you don’t have either one. Consisting of a quad op amp, a logic gate, a pushbutton switch, a debounce circuit, and a D flip-flop, the circuit generates 500-Hz bursts of one, two, or three pulses.
 Figure 1. A serial-pulse generator can be jumper-programmed to produce one, two, or three pulses. |
(a) (b)  (c)  Figure 2 The Figure 1 circuit operates with (a) single pulses, (b) double pulses, or (c) triple pulses. The waveforms are the U1B output (top), U1D output (middle), and U4 output (bottom). |
In the oscillator section, the integrator (U1A) produces a triangle wave at its output (Ref. 1). That, in turn, enables U1B to produce an output square wave with a 50% duty cycle.
In the switch-debounce and timing-latch section, pushbutton switch S1 connects to a switch debouncer (U2), which provides a noise-free output signal for driving the D flip-flop. The D-input logic level passes to the Q output only on the rising edge of the CLK signal. The one-shot section is also timed with the rising edge of the CLK signal. The one shot forces the output pulses from U4, whether single or multiple, to have the same width.
In the one-shot section, a third op amp from U1 sets the number of pulses that the circuit will generate. The flip-flop output pulls the C4 voltage high, driving the positive input of U1D high. The U1D output then goes high, and sets the voltage on its positive input via the R8/R9 divider. Current through the R10-R13 network and C5 then produces an increasing voltage across C5 as it charges. When the voltage at U1D’s negative input exceeds that of its positive input, the U1D output goes low.
The output signals from U1B and U1D connect to an AND gate, whose 500-Hz output persists for an interval that allows just the number of pulses required. Figure 2 shows the waveforms associated with one-, two-, and three-pulse outputs. Two jumpers (J1 and J2) set the number of pulses by altering the value of C5. Leaving both J1 and J2 open allows one pulse at the AND-gate output, closing (shunting) J1 only allows two pulses, and shunting both jumpers allows three pulses.
|
|
| Reference |
|
No related content found.
- 0 rated items found.
Datasheets.com Electronic Parts & Inventory Search
185 million searchable parts
- Part Number
- Description
- Inventory
- Products
- Manufacturers
View All Webcasts
