3-D chips, outreach to designers among highlights planned for 2009 International Test Conference
The 40th International Test Conference is scheduled for November 3 to 5 in Austin, TX.
Rick Nelson, Editor in Chief -- Test & Measurement World, 9/17/2009 9:31:00 AM
Boundary scan, testing of 3-D chips, yield vs. quality, and outreach to the design community will be among items on the agenda at the 40th International Test Conference, scheduled for November 3–5 in Austin, TX, according to program chair Bill Eklow of Cisco Systems. Activities include 55 papers presented in 18 sessions along with six lecture and advanced industry practices sessions. A poster session combined with a "Texas beer blast" reception will provide an opportunity to present late-breaking results and get feedback on innovative methods.
The Tuesday-through-Thursday conference and exhibition will be complemented by full-day tutorials Sunday and Monday (November 1 and 2) and workshops beginning Thursday evening and continuing through Friday (November 6). The advance program and registration information is available at www.itctestweek.org.
Antun Domic, senior VP and GM of the implementation group at Synopsys, will deliver a Tuesday keynote address titled "Design- and Manufacturing-aware Test Is Our Future," which will highlight the interdependence of design, manufacturing, and test, and he will describe how design, manufacturing, and test can join forces to meet the nanometer challenges. Following the keynote, Shekhar Borkar, Intel Fellow, will present an invited address titled "Design and Test Challenges for 32 nm and Beyond," in which he will emphasize that design for test will not be sufficient, with test hardware having to become part of the design itself.
Program chair Eklow discussed this year's conference in an interview.
Q: What's different about this year's program?
A: This year the program committee has created an entire new track for embedded tutorials on Wednesday, which complement the two days of tutorials on Sunday and Monday. Last year the program offered a couple of embedded tutorials around 7:30 a.m.—so people had to get up really early. Even though those tutorials had pretty good attendance, the steering committee wanted to expand the educational opportunities available during the conference to widen the educational opportunities, and let everyone sleep in a little bit.
Q: What topics will these embedded tutorials cover?
A: One will cover the testing of 3-D chips, which is a big topic in the program. The conference also includes a panel discussion on the subject. Another tutorial will cover emerging boundary-scan standards, and we will have a session on jitter fundamentals, and another on reliability.
Q: What else is new?
A: One idea we are trying out this year is what I'll call a "workshop in a session." It's a very interactive session, where we've purposely kept the presentations very short so that we could have a lot more time for discussion. We are trying this approach on a session related to ITRS roadmap for adaptive test. We've got good speakers there who are going to give very short presentations, and we've got a great moderator in Phil Nigh from IBM who is very good at provoking discussion.
Q: Why this new approach?
A: Typically, with paper presentations, the discussion is very one sided. You'll have a presentation that takes about 25 minutes out of a 30-minute slot, and the audience gets maybe five minutes of question-and-answer. This approach is necessary for the speaker to convey the work. Unfortunately, there is the potential that you could get a great discussion started but have to cut it off after that five minutes. A lot of times those discussions continue after the session, and they are great discussions, but there's only a small number of people involved and not the whole audience.
Q: I see there is a career track this year.
A: Yes, and that's thanks to the people at IEEE-USA and Marvin Weilerstein of the Philadelphia section. They set up a career track, which will be run on Thursday morning. It will include three sessions that will give people ideas on how they can either enhance their careers or possibly even go off and start a new career.
Q: Are you trying to reach out to other constituencies?
A: Yes. One suggestion we got from last year was to try to be a little bit more inclusive of the design community at ITC. So we are gradually easing our way into that. We have included sessions on silicon validation and reliability, which are areas where I think we do have some overlap between the test and the design community. I'm not sure how many design engineers we going to attract this year, but what we are trying to do is open the door. It's progressing slowly, but I think people are starting to realize that we do have this overlap with the design community and we should really be a little bit more inclusive. There are some good ideas out in the design community that could help influence the test community as well.
Q: The panel session is always popular.
A: Yes, and this year, instead of having a single panel time slot with five or six panels, we've spread the panels across three time slots—basically, the last session of each day, which will include two panels. The thought here was that we could give people the opportunity to potentially participate in more of these panel sessions. One of the pieces of feedback that we got was, "hey these panels are great but there are two or three of them that I really wanted to see and I could only sit in on one." By splitting them up we are hoping to give people better opportunities to be able to participate in more of them.
Q: How much participation from academia is there this year?
A: We got tremendous participation from the academics this year. We got high number of submissions from the universities and consequently a high number of accepted papers from the universities as well. And we are introducing a best academic paper for papers that list a student as first author.
Q: You mentioned boundary scan as a hot topic. Is that with respect to board test or the emerging IJTAG standard for chip test?
A: Both—we are covering anything that has a boundary-scan controller either onboard or inside a chip. There's an embedded tutorial on new boundary-scan standards—one, IEEE 1149.7 that just got approved, and another, the IEEE P1687 or IJTAG, which is still in development but is a hot topic among a lot of people. We've got a full boundary-scan session as well in the program. So, boundary scan popped up as a hot topic both from the submissions and from the fact that we had some interesting cases that we thought would make good presentations in an embedded tutorial.
Q: You mentioned 3-D chip test as a hot topic this year.
A: The interesting thing about that is that it actually connects the board-test and the chip-test people together, because with these 3-D chips, there are a lot of board-test techniques that need to be employed as well as some of the more traditional chip-test techniques.
Q: Are there any other topics that stand out this year?
A: One area of interest to me is the concept of the tradeoffs between yield and quality. I'm not sure how it will play out, but I can tell you that during the submission and review phase, there were some papers covering this concept, which generated some fairly lively discussions amongst the program committee. The topic will be addressed in a couple of paper sessions and also in a panel.
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