Test Ideas: DMM handles logic nanosecond-pulse-width waveforms
Use a flip-flop to square a narrow-pulse waveform.
By Marián Štofka, Slovak University of Technology, Bratislava, Slovakia -- Test & Measurement World, 10/1/2009 2:00:00 AM
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When testing sequential-logic circuits, you may find that, although the repetition rate of a logic signal is within the range of your DMM (digital multimeter), you can’t measure it. The displayed frequency value is either dubious or chaotically changing in time. The DMM may also behave as if there were no signal.
Any of these undesired states might appear when the duty cycle of the measured waveform is either close to 0 or is approaching 1. This problem occurs because you can’t expect a DMM with an upper frequency limit of perhaps 200 kHz to measure 100-ns-wide pulses, even if the repetition rate of these pulses is well below the upper limit of the DMM’s frequency range and is perhaps just 5 kHz. For a rough estimation of bandwidth for measuring a pulse width of 100 ns, consider this pulse to be a half-period of a square-wave signal. Use the following equation to calculate the required bandwidth:
This frequency is well beyond the bandwidth of most DMMs.
The second cause of failing to measure the repetition rate of logic waveforms with duty cycles that are too low or too high lies in the internal AC coupling of the DMM during frequency measurement. Thus, the decision threshold of an internal comparator, which you derive from the mean value of the measured waveform, is close to either the low level or the high level of the waveform. In the case of narrow pulses, the operation of the internal comparator becomes ambiguous, as any noise in the measured waveform or any noise that the comparator itself generates may cause an error.
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Figure 1. A binary divider turns low- or high-duty-cycle waveforms into square waves so you can measure their frequencies. |
You can address the problem by placing a binary divider between the source of a logic signal and the DMM. The binary divider comprises IC1, a positive-edge triggered, D-type flip-flop (Figure 1). The supply pin of IC1 connects to the supply terminal of the tested logic circuit. Therefore, you can run the logic at any industry-standard supply voltage of 1.2 V, 1.5 V, 1.8 V, or 2.5 V. If you use 3.3-V logic, use an external 2.5-V source to supply IC1. The internal protective diodes at pin 1 of IC1, along with resistor R1, reduce the voltage swing at pin 1 to an acceptable level in such a case.
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Figure 2. The flip-flop output, Q, produces a signal with a 50% duty cycle. |
A square-wave signal is at the output of the binary divider (Figure 2). The DMM no longer sees nanosecond pulses at its measuring terminal. You then must multiply the displayed frequency value by two to obtain the correct frequency. Due to relatively low values of R1 and of the flip-flop’s input capacitance (CIN, approximately 2.5 pF) at the device’s clock input, you need not worry about frequency compensation. The time constant of R1 x CIN is just 0.25 ns. The width of pulses at the input of the circuit can be as low as 1 ns.
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This article first appeared in the August 20 issue of EDN. |
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