ITC 2009: BIST to give way to built-in self-everything as 3-D chips emerge
Erik Volkerink of Verigy says that 3-D chips will be a hot topic at this year's conference, and he also describes the ITC's outreach to the design community.
Rick Nelson, Editor in Chief -- Test & Measurement World, 10/8/2009 12:59:07 PM
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Are fundamental changes needed in test? That's a question sure to stir controversy at the 40th International Test Conference, scheduled for November 3–5 in Austin, TX, according to ITC program vice chair Erik Volkerink, chief scientist at Verigy. Volkerink said that in an invited plenary address, Shekhar Borkar, Intel Fellow, will contend that "business as usual" will no longer be the order of the day, with current design-for-test and design-for-manufacturing methodologies becoming inadequate, requiring that test hardware become part of the design itself.
Volkerink echoed the contention of program chair Bill Eklow of Cisco Systems that test of 3-D chips is a hot topic this year, and he also emphasized the ITC's outreach to the design community in an effort to solve test challenges. Volkerink, who will be program chair next year's ITC (November 2-4, 2010, in Austin), said the 2010 conference will emphasize design even more. I spoke with Volkerink about issues facing the industry that ITC is addressing.
Q: What are the hot topics at this year's ITC?
A: Shekhar Borkar's address during the Tuesday plenary session is sure to stir controversy. His talk will be complemented by a keynote address from Antun Domic of Synopsys. He will also contend that as we reach the 32-nm node and start planning the jump to the 22-nm node, fundamental challenges are emerging that will force a rethinking of the role of test.
Q: When I spoke with Bill Eklow last month, he said that 3-D chip test would be a hot topic.
A: This year, we have quite a lot of papers related to 3-D. The technical program covers topics pretty much across the board, but if I had to pick one theme, it might well be 3-D.
Q: Is 3-D real, or is it mostly of academic interest?
A: I think it's clear that this is happening. We [on the program committee] have seen some compelling papers with real data points from big companies making real prototypes. People have done research to forecast how many TSVs [through-silicon vias] are expected to be required to deliver the next generation of Moore's law.
Q: What are the test challenges associated with 3-D and TSVs?
A: It's still uncertain what the impact on semiconductor test will be. There will be many questions, like what kind of probe-card technology would you want to use? TSVs are small and hard to probe, and they don't have ESD [electrostatic discharge] protection or matching circuitry, so connecting to them with a normal probe card might be very challenging. Also, the drive strengths of the op amps [within 3-D devices] are limited. They are really parameterized to drive to the layer, and so they are not parameterized to drive a whole probe-card/interface/tester.
Q: Bill Eklow also mentioned boundary scan.
A: Boundary scan is gaining traction and is related to the 3-D discussion we just had. I gave a talk recently in Taiwan about 3-D testing, and the analogy I used was Taipei 101 (en.wikipedia.org/wiki/Taipei_101). The building's combinations of doors and elevators make it a nontrivial task to end up where you want to be.
It's similar with testing 3-D chips, except you have thousands of elevators, and not all of them go to all the floors. We face a new paradigm in trying to establish a JTAG instrument-communication infrastructure that will let me access test data in a user-friendly fashion, and that will have implications for ATE.
Q: What other areas will the conference focus on?
A: I think one of the interesting topics for me is not so much digital test but RF and analog, where there's an opportunity to really improve DFT [design for test] and BIST [built-in self-test], and we will have some interesting papers on that. The logic industry has made a lot of progress over last decade; compression is very well accepted. But for RF and analog, you'll mostly find point solutions.
Q: I notice that the program committee has been reaching out to the design community. Why the emphasis on design?
A: If I look at the area of semiconductor test, there are three pillars that are crucial and that ITC can address. First is to gain the ability to really understand and address future test requirements, and that will involve input from designers. Second is to learn what are the latest technologies out there, such as structured ASICs and FPGAs, that can be used as building blocks for ATE systems. The third pillar is to learn methodologies and state-of-the-art technologies available today that we can use to test in the future--meaning five years out, because it takes two to three years to build a new tester, and it then has a lifetime of three years. Those notions will be visible in this year's program, and we will to emphasize design aspects more than we have done in the past.
Q: How can we use today's technology to test devices developed five years from now?
A: We are going to have to learn to adapt DFT, DFM, DFX, DF--everything to bridge the gaps between what state-of-the-art technology can deliver today and what the designs of the future will require in the way of test.
Q: What role will BIST play?
A: It's quite amazing how the library of built-in self test keeps expanding. Maybe you should call it BISX, to encompass built-in self-test, built-in self-diagnostics, built-in self-yield learning, and built-in self-everything. And ATE systems will need to be able to efficiently communicate with on-chip BIST engines, and doing that effectively will require input from the design community.
Q: What about the analog and RF design communities?
A: I think it's very important to reach out to them, so we can improve how we test analog and RF devices in a cost-effective manner and learn about future test requirements. The analog EDA world is emerging. [See "Handcrafted analog gets automated assist" and "Simulation gets speed, capacity boost."] There are initial commercial tools available, and as soon as they gain traction, I can imagine certain DFT techniques and built-in self -test techniques for analog might become more pervasive, if it becomes technology-node independent. The tools might become less like point solutions and more like a generic solution. ITC can play a leading role to report on the progress that goes on there.
Q: Are there any other key topics?
A: Another angle is silicon debug. If you look at the cost of bringing up a device, a significant portion, 20% according to some reports, goes into the post silicon debug. And so we have some interesting papers about that this year. I think going forward in the next technology node some of those challenges become even more severe. So, my guesstimate is that once we go though this exercise and prioritize the various topic areas for next year, I'm sure this is going to come out as one of the areas where the design community and the community at large will be interested in seeing more papers.
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