Mentor focuses on complementary DFT and BIST tools
Mentor Graphics rationalizes its logic BIST, ATPG, and test-compression offerings.
Rick Nelson, Editor in Chief -- Test & Measurement World, 11/1/2009 1:00:00 AM
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Mentor Graphics, with its acquisition of LogicVision last summer, is uniting BIST (built-in self test), ATPG (automatic test-program generation), and compression within its Silicon Test Solutions group. The move lets Mentor tout LogicVision’s SerDes and PLL BIST (phase-locked loop BIST) tools while allowing Mentor to rationalize its logic BIST and ATPG and test-compression offerings.
Stephen Pateras, BIST product marketing manager at Mentor, described the evolution of LogicVision that led to the acquisition. LogicVision had long had a BIST tool that used delay elements to measure jitter on a PLL. The technology imposed difficulties at layout, however, and Pateras said it had limited success.
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The ETSerdes BIST capability employs ULTRA technology to provide parametric, embedded test for SerDes devices. It makes use of a normal reference clock (fREF) and an off-chip frequency-offset clock (fREF2) that result in receiver undersampling. |
LogicVision then developed a technology to address high-speed serial I/O and presented papers on the topic, including one that won the Ned Kornfield Best Paper Award at the 2005 International Test Conference (Ref. 1). Called ULTRA (unlimited time-resolution analysis), the technology permits “accurate measurement of different forms of time-based variables,” Pateras explained, adding that ULTRA is the basis of the SerDes test product (figure). That product, he said, is “a fully digital, synthesizable, RTL [register transfer level]-based solution, so there is no need to deal with layout.”
ULTRA permits subpicosecond-accuracy measurements of SerDes parameters such as jitter, jitter tolerance, duty cycle, and rise and fall time. In applying it to SerDes operating at 1 or 2 GHz and higher, Pateras said it became apparent that the technology would be practical for testing lower-speed time-based signals, and Logic-Vision adapted it to test PLLs, replacing its original PLL offering.
On the logic side, Pateras said Mentor will move forward with the LogicVision BIST capabilities while supporting original Mentor BIST customers. Logic-Vision had comprehensive logic BIST, memory BIST, and boundary-scan tools, he said, adding, “The goal with the acquisition was to leverage those capabilities,” which will complement Mentor’s FastScan ATPG and TestKompress test-compression tools.
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Pateras said he expects scan- and BIST-based tools to coexist and pointed to past cooperation between LogicVision and Mentor. “The impetus for this acquisition was work we [at LogicVision] had been doing with Mentor on the logic side,” he said. “We had developed a product called ScanBurst, which essentially integrated our logic BIST at-speed scan infrastructure with TestKompress, and we already have customers using LV logic BIST and TestKompress together within the same core. We see it as combining forces and providing the most comprehensive solution for our customers.”
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