ITC 2009 panel explores future of analog test
Is there any way for the EDA industry to help accelerate the testing of analog and mixed-signal circuits?
Ron Wilson, EDN Executive Editor -- Test & Measurement World, 11/6/2009 1:44:05 PM
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A panel discussion at the 2009 International Test Conference in Austin, TX, (November 1–6) explored a question critical to the continuing integration of analog functions into SOCs (systems on chips): is there any way for the EDA (electronic design automation) industry to help accelerate the testing of analog and mixed-signal circuits? Panelists from both the semiconductor and EDA industries contributed.
Craig Force, test engineering platform manager at Texas Instruments, opened the discussion by stating what would be the defining distinction for what came later. "We have to redefine the problem," Force said. "For purely analog components in the past, test has meant parametric test of everything on the data sheet. But in our environment we are not characterizing, we are trying to verify that the circuit is built right. The problem is not to measure parameters but to find defects."
Force listed several promising strategies for making this transition. First, he said, test engineers need to map their familiar parametric space into a testable space. In some cases, that means modeling large, multitransistor analog systems as behaviors rather than as networks of components. A problem with this approach today, he commented, is that today there are too many languages for modeling analog systems, harming the portability of the work. Another suggestion Force offered was to bundle analog signals into a digital pattern that could be accessible to test systems. The object of these reductions, he said, was to find digitally-accessible patterns that would indicate defects in the analog circuitry.
Qualcomm senior director of engineering Karim Arabi spoke next, pointing out that in his world of very large SOCs, analog circuits make up a small portion of the nodes, but 70% of the test cost and 45% of the test development time. And he said that in a way, analog had become a misnomer. "Pure analog is not visible in SOCs today," Arabi said. "Analog circuits are heavily infiltrated with digital controls."
Arabi continued that one of the primary problems is that two of the fundamental building blocks of a test strategy are missing: there is nothing equivalent to automatic test-pattern generation for analog, and that is in part because there is no practical fault model for analog, despite years of work. DfT and BIST are showing up here and there for analog circuits, he said, but they are custom efforts for each circuit.
Arabi closed with a series of warnings to his compatriots in the EDA world. "Don't try to automate DFT [design for test]or production test-vector generation until you have succeeded in automating analog design," he warned. "And don't offer us a solution that automates 80% of the process. The 80/20 rule always undermines that. And don't try to get us to use a fault model that the industry hasn't accepted."
Concluding, he said, "I believe startups will drive the progress in this area. I don't see a major role for the big five vendors in the next three years."
Opening the discussion for the EDA vendors, Steven Sunter, engineering director for mixed-signal DFT at Mentor Graphics, echoed much that the chip designers had said. "What we are looking for is the analog equivalent of scan. But first, we need an accepted fault model. I worry that an accurate model for analog may be impossible—but we can't let that hold us back. We need to get a good-enough model. And we must separate the issue of characterization from the search for random defects."
In the search for the good-enough practical solution, Sunter offered what may be an outline of the program that test company LogicVision was working on when acquired by Mentor. "I think we should agree on a few basic techniques. Use loopback, and employ a low-frequency analog bus in cases where that will work, both controlled by 1149.1. In addition, use sigma-delta converters to in effect convert voltage into time intervals—that's the only way to manage the huge dynamic ranges you encounter in analog circuits. And then use a high-frequency serial bus to get the digital data off the chip."
Synopsys scientist Rohit Kapur, who pled for forbearance on the grounds of being a digital guy who had been drafted to replace the planned speaker, pointed out that chip designers have already devised custom solutions, such as eye-diagram generators for SerDes IP blocks. At the risk of antagonizing a part of the audience, Kapur offered, "The solution is to digitize the analog. But to do that today, you must understand the application and do a custom design. But can we find a generic way to do that, independent of the function? If so, EDA can automate it." In order to make progress, Kapur suggested, we should forget about trying to find a fault model. "Just treat the analog section as a black box," he advised.
Cadence's VP for Encounter Test Sanjiv Taneja agreed with Arabi that the problem today is testing mixed-signal circuits, not purely analog ones. And he warned that the problem was only going to get worse as geometries continued to shrink and variations continue to grow. But he differed from some earlier speakers by maintaining that fault modeling was necessary, as was accurate simulation. And he said that in the end, analog test must confirm conformance with specifications, not just detect recognized faults. As a note of hope, he pointed out that the trend toward self-calibration and self-adaptation in AMS design might actually help make automated test solutions possible.
The panel was effectively unanimous on the need to produce tools to automate the test generation and application processes for analog/mixed-signal circuits. But there was less unanimity on just how—and whether—we would get there. As a rule of thumb, based on the comments of the panelists, watch the start-ups. And keep an eye on the mixed-signal DFT group from LogicVision, now resident in Mentor Graphics.
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