ITC 2009: New failure mechanisms, analog, and adaptive test
International Test Conference, November 2–5, Austin, TX, www.itctestweek.org.
-- Test & Measurement World, 12/1/2009 2:00:00 AM
Forward-looking issues grabbed center stage from the start of the International Test Conference this year, beginning with the keynote addresses. Antun Domic, senior VP and GM at Synopsys, described the parallel evolution of test challenges and test tools. Challenges, he said, had progressed from finding stuck-at faults to fighting test complexity to wrestling power and timing in test circuits to—tomorrow—facing whole new kinds of faults. In response, Domic suggested, tools have evolved from being point solutions, to offering test-aware synthesis, to integrating test into design flows to fight power and timing issues. Tomorrow, he said, these full test flows will require timing, physical design, and process information as well.
Looking even farther ahead, Intel fellow Shekhar Borkar described the chip of the future: a massive mesh of small soft IP blocks, each with fine-grained voltage scaling, operating near the transistors' threshold voltage. The resulting soft error rates, added to extreme process variations and aging effects, would render factory testing meaningless, Borkar said. Instead, designs would have to self-test on the fly, and then self-calibrate and reconfigure. This view upends the traditional role of test in the design flow entirely.
Later, in an analog session, panelists queried whether analysis could collapse a full parametric sweep into a set of point measurements, and whether such concepts as built-in self-test and structural test—fundamental in the digital world—could apply to analog circuits. The answers depended on accurate analog fault models and much better R&D funding.
In an adaptive test panel, panelists first tried to define adaptive test, homing in on the ability to eliminate tests from the program based on the emerging statistics from previous tests. One debate that sprung up was whether or not adaptive test—based as it is on histories of individual chip test results—required each die to have a unique serial number.
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