Test Ideas: Sort thyristors with a test circuit

Use this circuit to sort for latch current and hold current.

By Chee Hua How, TDK Malaysia -- Test & Measurement World, 2/1/2010 2:00:00 AM

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Thyristors conduct current from their anode to cathode (I_AK) when they receive a gate pulse of sufficient current and duration. They will continue to conduct if I_AK reaches the latching current (I_L) level even after the gate pulse ends. The device should remain on as long as I_AK exceeds the device’s hold current (I_H). If I_AK falls below a minimum I_H level, the thyristor should turn off.

Thyristor data sheets will specify typical values for I_L and I_H, but you may need to sort thyristors based on the difference between I_L and I_H—not their individual values—to ensure that the thyristor will properly control a circuit. If you ignore the variation of these two parameters, the thyristor may cause a product failure should it fail to properly turn on or off. Thus, you may need to set limits that guarantee proper circuit operation.

Figure 1. You can use this circuit to sort thyristors based on I_L(MAX) and I_H(MIN).

The circuit in Figure 1 lets you set values for I_L(MAX) and I_H(MIN) that will ensure proper product operation. I_L(MAX) and I_H(MIN) are two extreme properties that never coexist in a single device. You can then use LEDs to indicate the thyristor’s pass or fail condition. Table 1 describes the four possible test results.

The settings in Figure 1 are for screening a TSN10A80 thyristor to fulfill requirements of I_L ≤ 20 mA and I_H ≥ 6 mA. The circuit uses a 20-mA current source formed by U1 and Q3. This current can then travel through the LED1 branch, through the LED2 branch, or through the series RC circuit (R9 and C3). A dual monostable device, U3, sets two clock pulses (CLK1, CLK2) that trigger either the DUT or Q5, provided the pulses are of sufficient length to guarantee that the respective devices turn fully on and off.

Figure 2. A timing diagram shows the relationships between the CLK1 and CLK2, which trigger the DUT and the circuit's two main branches.

Start a test by pressing switch S1, which forces Q2 off and thus forces Q1 off. That momentarily removes V_CC (20 V) from the circuit (Figure 2). Following a short delay t_DLY1, the first firing signal, CLK1, goes to the DUT (device under test) to turn it on. The DUT will conduct the entire 20 mA from U1, which will illuminate LED1. Q4 and Q5 will not conduct because CLK2 is low.

After period t₁, U3A will remove the gate pulse CLK1 from the DUT. A blanking time of t_DLY2 will follow. The RC network R11 and C4 set the blanking time, which is the period in which the DUT should latch in its conducting state. If the DUT fails to latch, it won’t conduct current and LED1 will extinguish (condition 1 of Table 1).

If the DUT latches, I_AK will be 20 mA and U2B will turn on, sending a trigger pulse to its triac side, U2A. After t_DLY2 elapses, U3B will initiate CLK2 and Q5 will conduct for period t₂. Q5 should then latch in its “on” condition. When Q5 activates, the U4-Q4-U2A network will divert 14 mA from the DUT branch. If the remaining current (6 mA in this example) of DUT current is below the DUT’s holding level, LED1 will extinguish and LED2 will remain on (condition 3 of Table 1). If not, the DUT has failed to turn off and both LEDS will remain on (condition 4 of Table 1).

The values shown in Figure 1 are based on measurements for the TSN10A80 thyristor. To use this circuit with another thyristor, you will need to adjust the duration of t_DLY1, Δt₁, t_DLY2, and Δt₂ by changing the values of R18•C6, R16•C5, R11•C4, and R17•C7, respectively, to change time constants. Proper timing of t₁, t_DLY2, and t₂ will ensure that the current flowing into the DUT reaches steady state before the firing signals (CLK1 and CLK2) time out.

Figure 3. A DUT failed to shut off because its current dropped from 20 mA to 6 mA.

Figure 4. A DUT passed when it properly shut off, dropping its current to 0 mA.

Proper timing also prevents excessive overshoot or undershoot current. The CLK1 and CLK2 pulse durations in Figures 3 and 4 show 105 µs and 120 µs, respectively (100 µs/div). The tall waveform in Figure 3 shows a failed DUT, while Figure 4 shows a passed device. In both cases, the DUT successfully latched (tall trace). In Figure 3, I_DUT dropped to 6 mA after CLK2 activated, diverting 14 mA through Q4 and Q5, but the DUT remained on. In Figure 4, I_DUT dropped to 0 mA, indicating that the DUT had shut off. Thus, the device tested in Figure 3 had a value of I_H(MIN)≤6 mA, but in Figure 4, I_H(MIN) > 6 mA.

TABLE 1. Test result state diagram

Condition	LED1	LED2	Result
1	Off	Off	DUT fails to latch
2	On	Off	Invalid; tester problem
3	Off	On	Pass
4	On	On	DUT fails to turn off

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