SOC DFT verification with static analysis

Verifying the connectivity of different IP blocks at the SOC level is usually done with functional simulation.

Marco Brambilla and Jean Philippe Loison, STMicroelectronics, and Kiran Vittal, Atrenta -- Test & Measurement World, 12/22/2010 12:00:00 AM

To achieve higher quality on multi­million gate designs and high-speed ASICs, manufacturers are relying on structured DFT (design-for-test) methodologies such as scan, at-speed test, scan compression, and BIST (built-in self-test). Typically, testability issues appear at the last stage of the design flow during ATPG (automatic test-pattern generation) or gate-level simulation. Even though this stage is close to tape-out, the engineering staff must go back and fix the original RTL (register-transfer-level) design for re-use and testability and then repeat the steps of the implementation flow, usually resulting in a large schedule impact.

An SOC DFT architecture requires complexity to achieve high-quality manufacturing test.

Many design teams use static verification checks and methodologies to catch testability issues at RTL for both stuck-at and at-speed testing. Yet, verifying the connectivity of different IP blocks at the SOC level—with respect to memory BIST, JTAG, or IEEE 1500 standards—is usually done with functional simulation. Test benches are not always best for verifying connectivity of the logic at the SOC level with signals from SerDes, PLLs, IEEE 1149.1/1500 circuits, and BIST logic that go to various blocks in the design.

Using functional simulation to verify connectivity has several disadvantages:

• Test benches are manually created and need several thousands of simulation cycles to put the design in a certain configuration for validation.
• The verification engineer must test all conditions, including both positive and negative cases, which is time-consuming.
• The default configuration through the test bench might be configuring some of the paths to be exercisable by chance and not by design.
•  As an alternative, STMicroelectronics has applied static techniques to verify different kinds of integrations in several SOCs using Atrenta's SpyGlass-DFT tool. Using static and formal verification methods to verify connectivity at the SOC level provides several advantages:

•  No test benches are required.
•  Assertions prove that the connections exist and the desired value is correct at internal nodes.
•  Run times are faster and debug is simpler and easier with highlighted target failure points.
•  This technique can be applied to new design revisions through regressions at both RTL and gates.

We describe this alternative process in detail in the full online version of this article.