IC package inspection gets complicated

Ann R. Thryft, Contributing Technical Editor -- Test & Measurement World, 7/1/2011 12:00:00 AM

Several trends in IC packaging, including changes in sizes and construction, are combining to make the inspection of packaged chips more complicated, difficult, and time-consuming. IDMs (integrated device manufacturers) and their subcontractors must inspect a wider range of package sizes and thicknesses, perform more substrate inspection for some package types, boost inspection accuracy, and increase the amount and accuracy of metrology.

The sizes of final packages are changing in two directions, said Pieter Vandewalle, senior director of marketing for KLA-Tencor’s ICOS Division. “There’s a trend toward larger packages for high-end applications, and another toward smaller, thinner, higher-performance packages, mostly for mobile applications,” he said. “Tools must now accommodate sizes from 2.5 mm x 2.5 mm to 66 mm x 66 mm.” As packages get thinner, it’s becoming more important to inspect warpage and cracks that may result from handling or testing them.

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High-end package interiors are becoming more complex, requiring more inspection, said Vandewalle. Inside a typical package, dies are bonded to the substrate with wire bonding. The trend is to place more dies in a single package. In lower-performance packages, the dies are attached to the substrate via wire bonding.

“In higher-performance packages there’s a shift to flip-chip attachment methods,” he said. “A flip-chip package contains multiple dies and even multiple packages, so the final package and the substrate must be inspected. In addition, metrology is required for the bumps on both the die and the substrate.”

CPUs and graphics processing units using this package type typically require 100% inspection of the substrate before the dies are mounted on it. The substrate’s bump area consists of up to 10,000 bumps or more, and those must be measured with an accuracy of less than 1 micron at a rate of 1000 to 4000 substrate units per hour, he said.

Another complex package type that’s becoming more common in logic and memory chips is package-on-package, said Vandewalle. Here, packaged ICs are stacked on top of each other using TMVs (through-mold vias), so the top side also has to be inspected using 3-D techniques. Other new technologies that increase inspection requirements include pre-mounted passives that require 2-D and 3-D techniques, TSVs (through-silicon vias) that must be inspected before molding, and dies embedded in the substrate.

To handle these IC packages, KLA-Tencor has combined the capabilities from several of its automated component inspection systems in the ICOS CI-T620, said Vandewalle. Its cost of ownership is lower and it is more user-friendly than previous generations of tools, he said, while the accuracy of final package inspection has been increased down to 5 μm via 3-D metrology. Downtime is minimized by a faster package changeover aided by dual tapers and a throughput increase of 70 to 80% over previous models. The system is designed for all tape and reel packages. T&MW

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