Camera Link HS moves forward

The new Camera Link HS standard is expected to be released in November 2011.

Ann R. Thryft, Contributing Technical Editor -- Test & Measurement World, 8/1/2011 12:00:00 AM

For a demonstration at Automate 2011, Silicon Software connected its prototype microEnable V Camera Link HS frame grabber board to Mikrotron’s EoSens 4CL HS camera. Courtesy of Silicon Software.

Progress continues on the new Camera Link HS standard, which the AIA (Automated Imaging Association) unveiled in a pre-release form at the Automate 2011 show (March 21–24, Chicago, IL). The AIA’s Camera Link committee first proposed a revision to Camera Link in late 2009 under the name Camera Link 2, and it used Dalsa’s HSLink technology as the basis for the standard (Refs. 1 and 2).

In April 2010, the AIA formed the Camera Link HS Committee to fine-tune the technology, and now, according to Mike Miethig, committee chair and technical manager for Teledyne Dalsa, the committee hopes to announce Release 1.0 of the standard in November at Vision 2011 in Stuttgart, Germany. (Dalsa was renamed Teledyne Dalsa after Teledyne acquired the company in February of this year.)

Although it carries the Camera Link name, the HS standard is actually a new type of interface. “The Camera Link HS feature set is very close to Camera Link’s, and its message types are the same, but the implementation and how messages are carried from one end of the cable to the other are totally different,” said Miethig.

Originally, Camera Link HS arose from the need for faster transfer speeds to accommodate 1-Gpixel/s time-delay-integration cameras in multi­camera systems, said Miethig. “That would require three Camera Link cables per camera,” he said. “But some of our customers use up to 20 cameras per system, which would mean 60 cables, far too many. So, we needed to find a method to reduce cable count.” He added, “Since we wanted to reduce wire count, we needed to put video communication, camera control, and high-speed trigger and GPIO on a single wire.” A serialized or packetized method transfers far more bits per wire than a parallel technology such as Camera Link.

Miethig also explained that the committee needed to create a standard that offers greater reliability. With Camera Link, sometimes there were bit errors on the cable. Camera Link HS needed to be 100% reliable under a single-bit-error assumption. “In [Camera Link HS], we have redundant trigger codes, as well as video hardware resend to guarantee 100% reliable data,” Miethig said. “This ability contrasts with the GigE serial standard, where you need a frame buffer in the camera for resend.” The Camera Link HS SerDes can be implemented inside an FPGA with external equalizer chips from multiple suppliers, and 100% reliable data is achieved with memory sizes that are small enough to be implemented inside the FPGA to reduce cost, size, and power.

The committee wants to carry forward as many of the features and functions of Camera Link as possible to Camera Link HS, said Miethig. “We want to preserve the strengths of Camera Link while also making sure it is a technology that can migrate to higher speeds,” he said. The protocol is therefore designed for a 10-Gbps SerDes, and can be scaled down to slower rates if necessary. Camera Link HS prioritizes messages and maintains the real-time low latency and low jitter of Camera Link, eliminating the need for a separate triggering cable. It supports both multicamera and multi-frame-grabber configurations.

“We’re currently finalizing the video and command channel packet structure to ensure that the order of bytes and the number of bits in video packet headers meet our roadmap,” said Miethig. The Camera Link HS committee has approved the SFP (small form-factor pluggable) fiber-optic connector. Fiber-optic cables cost about the same as coax and can be up to 300 m long. The committee is also considering alternate copper connectors and copper-to-fiber adapter modules, as well as power-over-copper cable. Features that may be included in Release 2.0, targeted for June 2012, include frame-by-frame windowing with the camera as master, intermediate device general-purpose I/O and data concentrators, and alternate transmission speeds, such as 10 Gbps.

Mikrotron and Teledyne Dalsa are sharing the VHDL IP (intellectual property) cores that incorporate the protocol with other committee members, which is unusual in standards development, said Miethig. “In addition, Matrox is writing testbenches to validate these cores, so when we make a design improvement, we can verify that we didn’t break features that were working previously. By sharing code and developing this infrastructure, we can reduce everyone’s cost of development.”

Products on display

At Automate 2011, demonstrations using pre-Release 1.0 products showcased the Camera Link HS standard’s increased bandwidth, extended cable lengths, and multiple cable and physical interface options. 3M debuted its Twin Axial Ribbon cable and announced plans for fiber-optic assemblies for longer transmission distances. Mikrotron introduced its 4-Mpixel, 500-fps high-definition EoSens 4CL HS camera. Silicon Software debuted its prototype microEnable V CLHS frame grabber.

During the show, Mikrotron’s new camera and Silicon Software’s new frame grabber were connected by a single 2-Gbytes/s Camera Link HS cable, said Michael Noffz, Silicon Software’s marketing director. The frame grabber’s onboard FPGA offloads processing from the host CPU, as demonstrated at the show by a 3-D laser triangulation application running on the FPGA.

Silicon Software’s prototype microEnable V Camera Link HS frame grabber is equipped with two CX4 camera inputs and an FPGA for onboard real-time image processing. Courtesy of Silicon Software. (Ref. 3.)

 
For applications that don’t require image processing on the frame grabber, Silicon Software has ported its DMA900 direct-memory access technology—capable of transferring up to 900 Mbytes/s in a 10-tap Camera Link configuration—to its new board. This allows the frame grabber to receive 10-bit packed image data from the Camera Link HS cable, unpack the data, and transfer raw images to the host PC at 3600 Mbytes/s. This “DMA3600” technology, like the DMA900 technology, uses one DMA channel to transfer image data to the host PC’s RAM, so the PC need not perform additional processing for image reconstruction, said Noffz.

Proof-of-concept products compatible with HSLink were previously released, including cables and cable assemblies from Hirakawa Hewtech and Components Express and cameras and frame grabbers from Teledyne Dalsa. The Teledyne Dalsa products will not be interoperable with Camera Link HS, but the other products will be, said Miethig.
 
REFERENCES


2. Camera Link 2, approved in March 2011, now designates a collection of changes to the original Camera Link. These include mini-Camera Link connectors, the PoCL (Power over Camera Link) and PoCL Lite interfaces, and the Appendix D cable specification.

3. This diagram was not included in the print version of the article.


FOR MORE INFORMATION

“Camera Link HS - The Machine Vision Protocol Moving Forward,” Automated Imaging Association.

Miethig, Michael, “Camera Link HS.”