IC tools show integration progress

Ron Wilson, Contributing Technical Editor -- Test & Measurement World, 11/1/2011 12:00:00 AM

Presentations at the 2011 International Test Conference (September 18–23, Anaheim, CA) illustrated the growing level of integration within the respective product lines of Mentor Graphics and Synopsys. This evolution is partly a result of continuing integration of acquired companies (Logic­Vision by Mentor; Virage Logic by Synopsys) and partly a result of initiatives within the two EDA (electronic design automation) firms to build bridges between design intent, physical analysis, test generation, and yield management.

Connections between design and test are increasing. Mentor director of marketing Greg Aldrich said customers are already seeing positive results from, for example, increased use of timing-aware ATPG (automatic test-pattern generation) that focuses its search for delay faults on the nets with the least timing slack. He said some customers are also beginning to use Mentor’s Calibre EDA tool to identify design-for-manufacturing hot spots in conjunction with LEF-DEF (library-exchange format/design-exchange format) layout data and silicon test results to zero in on yield issues early in the manufacturing cycle. Freescale Semiconductor, Aldrich said, has been able to extract significant data from as little as a few hundred dice in this way.

But Aldrich admitted that for many design teams, these are still leading-edge capabilities. Some of the biggest gains in SOC (system-on-chip) test productivity today, he said, are still coming from test compression, which has reached compression ratios of over 100.

In the near future, Aldrich projected, we will see on-chip test-compression logic merge with the logic for built-in self-test, increasing compression ratios further and improving coverage. And he suggested that test-pattern generation would become more closely associated with individual IP blocks rather than be seen as a full-chip task. This would allow test engineers to reuse patterns from previous instances of the IP, and to construct hierarchical test schemes to deal with very large SOCs.

Synopsys, meanwhile, continues to leverage its dominance in synthesis to strengthen its test offerings, gathering synthesis, scan insertion, timing closure, and ATPG into a single process. Synopsys marketing manager Chris Allsup said that integration of Virage’s STAR (self-test-and-repair) Memory technology into the flow now allows the company to generate a single controller for STAR, logic test, and boundary scan. In addition, Synopsys described automatically reusing shift registers for scan and using the scan chains within STAR Memory instances in the testing of surrounding logic.

Synopsys also emphasized the value of providing timing-slack data to the ATPG tool to improve detection of delay faults. This becomes particularly important, Allsup suggested, when synthesis optimizations aggressively manipulate the logic design in order to close timing.

Both companies also discussed the importance of preserving designers’ power intent while creating scan chains and patterns. Insertion and ATPG tools must be aware of power-domain crossings, especially in SOCs with dynamic voltage control. The fact that timing slacks may change in different power modes adds another dimension to the problem. And of course, the tools must explicitly test level shifters, power gates, and power controllers.

Altogether, both companies described an increasing flow of increasingly complex data between design tools, insertion tools, and ATPG tools on the front end. For the back end, both emphasized the growing convergence of design-analysis data and diagnostic-test data to identify yield issues. T&MW

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