Distributed test strategy cuts costs

Although substantial improvements have been made to ATE in the last decade, the changes haven't come close to matching the enormous increases in device complexity. The cost to fabricate a transistor has fallen dramatically, from one-tenth of a cent in 1983 to less than one-thousandth of a cent today (Figure 1), according to the Semiconductor Industry Association (SIA) (Ref. 1). At the same time, the cost of testing each transistor has remained relatively flat at around one-ten-thousandth of a cent. At the SIA's projected rates, it would soon cost more to test a transistor than to fabricate it.
 

The cost of test equipment remains high because of the semiconductor industry's heavy reliance on at-speed functional testing. Each generation of ICs brings escalating pin counts plus the need for higher speeds and accuracy, so manufacturers frequently must replace their installed base of test equipment.

At the same time, ICs exhibit a marked reduction in economic life, often becoming obsolete in 12 months or less. Because it is more important than ever to reduce the time to market, manufacturers must find ways to reduce the amount of time that is devoted to test. The time spent generating test vectors with suitable fault coverage for manufacturing tests now takes up 40% or more of the IC design cycle—more than any other step (Figure 2). Your time allotment may vary depending on the device type, but unarguably, developing functional-test vectors is a daunting task.

Figure 2. According to one estimate, test-vector generation takes up 40% of total design time.

As design complexity increases, so does the time required for manually generating functional test vectors. At the 1999 International Test Conference, Intel's Pat Gelsinger, in his keynote address, stated that each new generation of microprocessor requires approximately twice as much manual test-generation effort as the previous generation (Ref. 2).

To overcome the challenges of testing deep-submicron ICs, manufacturers need new thinking as well as new equipment. Many manufacturers perform both structural and functional tests on a high-end, general-purpose tester, an approach that leads to large capital investments, poor capital productivity, and rapid system obsolescence. What is needed is a shift to a distributed testing strategy that moves lengthy structural tests from expensive ATE to lower-cost design-for-test (DFT) platforms. Such a shift would reduce equipment costs and shorten lead times, helping manufacturers keep pace with increasing design complexity.

Why separate the tests? Functional tests ensure that a device is operating correctly. Structural tests ensure the correct fabrication of the basic elements such as wires, gates, and transistors. Structural tests are based on fault models that target defects that may be present in the device under test (DUT). The fault simulation and automatic test-pattern generation (ATPG) usually occur at the gate-level-model abstraction level and simulate the existence of specific faults, such as being stuck-at V_DD (a logical 1) or ground (a logical 0). The goal of fault modeling is to model as high a percentage as possible of the actual physical defects that can occur in a device. This reduces the number of individual defects that have to be considered.

Functional testing requires a large number of tester channel I/O pins that can drive and compare at device speeds, typically with high levels of timing accuracy. This is one reason why the cost of testing a transistor has remained relatively flat. On the other hand, if a device incorporates the right kind and amounts of DFT, structural testing can be done with far fewer tester channels that have significantly less speed and less accuracy. As a result, structural testing can be performed on a tester that is considerably less expensive than that required for functional testing, possibly letting you reduce the number of high-cost ATE systems you need.

In addition, structural testing requires far fewer engineering resources than functional testing, which remains for the most part a manual process. For devices that incorporate scan-based DFT, ATPG algorithms typically can generate structural test patterns within hours, as opposed to the weeks, months, or years of manual effort required for functional test (Figure 3). And with structural testing, you can generally reuse scan vectors in system-on-chip (SOC) cores.

Scan is the bedrock on which most other DFT techniques are built. Scan-based designs sacrifice some silicon real estate and some performance for the sake of making the device more testable. In large designs, this overhead is quite acceptable.

Figure 3. Intel has found that each new generation of microprocessor requires approximately twice as much manual test- generation effort as the previous generation.

Figure 4. Test-chip failure analysis indicates that 100-kW bridges contribute significantly to defect populations that cause faults—related to VDD, temperature, and frequency sensitivity—that can’t be modeled as stuck-at faults.

I_DDQ measures the static current a device draws. Many defect types, such as resistive bridges, cause the static current level to be greater than it is on a device that doesn't have the defect.

All of the above-mentioned techniques—as well as various ad hoc DFT techniques—use the scan chains for test-vector delivery to the DUT.

The single stuck-at fault (SSAF) model is by far the most commonly used. The SSAF model covers many of the possible manufacturing defects in CMOS circuits, such as missing features, source-drain shorts, diffusion contaminants, and metalization shorts. On the other hand, the 1999 International Technology Roadmap for Semiconductors (ITRS) makes the point that SSAF models cover only about 70% of the possible manufacturing defects that can occur in CMOS circuits (Ref. 3). DFT-savvy users also use other fault models to find defects not detectable by the SSAF model.

For example, the frequency of bridging defects, which aren't addressed by SSAF models, is increasing as process rules shrink. For instance, a recent study showed a dramatic increase in the proportion of 100-kÙ bridges (Figure 4), which cause parametric delay defects, as the process rules changed from 0.25 µm to 0.18 µm (Ref. 4). In addition to bridging models, other models are coming into play, including open fault models, transition-delay models, path-delay models, and I_DDQ models (Ref. 5).

Both delay and open fault models increase the number of scan vectors that are required, because these classes of faults normally require vector-pairs in order to sensitize and detect the faults. I_DDQ models are less demanding with respect to scan-data volume, yet they impose their own problems, such as fixturing constraints and the difficulty of determining the I_DDQ pass/fail threshold.

Increasing device complexity and the growing importance of having better tests for opens, resistive open defects, and bridging defects conspire to guarantee that more structural tests will be needed to maintain device quality. These tests are primarily applied through the scan chains, causing the scan data volume to possibly grow exponentially with device complexity (Figure 5).

Figure 5. Scan-data requirements rise exponentially with gate count.

Of course, the growing scan data volume will materially lengthen test times. If you employ logic BIST instead of deterministic scan vectors, the scan-data volume may go down, but the number of clock cycles (which directly relates to test time) won't; indeed, it could go up because of the way cumulative fault coverage builds up with cycle count with logic BIST.

The relative performance of functional tests and the flavors of test vectors generated by different fault models, delivered through scan-based structural tests, were addressed by a Sematech study (Ref. 6) that was designed to compare four different test methods: scan-based stuck-at fault test, functional test, I_DDQ test, and delay test (transition fault model) in a standard-cell ASIC. The ASIC used for the study had 116,000 logic circuits, a 0.45-ìm effective channel length, and three levels of metal; it operated at 40 and 50 MHz. The following tests were applied to each device:

• 8300 stuck-at fault patterns with 99.7% SSAF coverage;
• 532,000 cycles of functional patterns with 52% SSAF coverage;
• 15,232 delay test patterns with approximately 90% transition fault coverage; and
• 195 I_DDQ patterns with 99% pseudo-stuck-at fault coverage.

Several thousand chips were used in the experiment; the results are shown in Figure 6 (the dies that passed all tests or failed all tests are omitted from the figure).
 

Several conclusions can be summarized from this study:

• The SSAF model alone is not sufficient.
• Near-100% SSAF coverage misses many defects.
• SSAF and delay faults have a large overlap in defect coverage. (This isn't surprising, because SSAF can be considered a subset of transition delay faults—the subset with infinite rise and fall times.)
• The I_DDQ threshold can significantly affect yield.
• Many (bridging) defects were detected only by I_DDQ (but the effectiveness of I_DDQ is diminishing for deep-submicron designs).
• Some functional testing is still required.

A closer look at the study highlights an opportunity for manufacturers to optimize their test coverage and capital investment by modifying the way they perform structural and functional tests. Current methods are becoming untenable as more structural testing—delivered through the scan chains—is needed to cope with increasing complexity and the new types of defects that are emerging in deep submicron (DSM) designs.

Of course, you could always add more structural tests to existing test programs, but test application times are already too long, and this would only make them longer. For example, an 8-s total test time for a high-end datacom SOC can easily contain 6.5 s of structural test application time (running memory BIST, I_DDQ tests, and scan-based vectors). In other words, 80% of the tester time is spent on nonfunctional or mixed-signal tests. The hardware that drives functional tester costs is unused most of the time.

What is needed is a distributed test strategy that separates structural tests from the expensive ATE used for functional testing. This would require the use of lower-cost test platforms for structural tests. These systems would interact with the device's DFT and BIST engines. You'd then need fewer conventional ATE systems for functional test, as the systems would be needed only to test the devices that passed the structural test suite.

You could implement this approach by performing structural test during wafer sort and performing functional test on packaged devices during final test. Of course, before deciding on a test strategy, you need to take into account the packaging costs, the test escapes from wafer sort, the test equipment, and automation capital investment.

The goal of structural test is to use scan chains and other embedded DFT to provide high levels of fault coverage to detect stuck-at, transition, delay, bridging, and I_DDQ faults. While stuffing test vectors into scan chains isn't a demanding task, structural testers nevertheless may require some high-performance options. Structural tests of some on-chip functions such as PLLs, for instance, might require a high-performance, low-jitter clock.

A structural tester also must be able to efficiently schedule successive tests without creating excessive overhead time penalties or wasting memory space. Such functions can facilitate the test of chips for which you may not be able to exercise all the scan chains simultaneously, either because of restrictions stemming from multiple DUT clock domains and the DFT implementations used or because of power-dissipation considerations. Furthermore, structural testers will require DUT power-delivery capabilities that can handle the higher than normal di/dt transients that occur when structural-test sequences cause simultaneous toggling of multiple nodes. Power-supply requirements will be particularly demanding in light of the scaled down V_DD and threshold voltages in DSM.

Moving to a distributed testing strategy is not easy. You must change your rules for DFT to make it possible to use lower-cost ATE platforms for structural testing. You also need to improve your defect modeling to maximize defect detection through structural test methods (minimizing the structural test escapes). Most importantly, all areas of the organization including management, designers, and test engineers must be ready to embrace the changes.