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FA leads to proper ESD tests

Analysis of device failures helps identify the best ESD model for GaAs ICs.

Amy Poe, Steve Brockett, and Tony Rubalcava TriQuint Semiconductor, Hillsboro, OR -- Test & Measurement World, 11/1/2001

What's an ESD model?

At our company, we used failure analysis (FA) to successfully determine what caused GaAs RF ICs to fail during retesting. In our case, the source of the damage turned out to be just as important as the damage itself. Our investigations show the importance of using the Charged Device Model (CDM) for ESD testing of small ICs in plastic packages. In fact, CDM testing proved invaluable in establishing the reliability of a GaAs radio frequency (RF) IC.

The problems we investigated originated when a sample of 200 good ICs was retested and nine of the devices failed the retest. The test results placed the reliability of all the ICs in doubt.

Figure 1. The GaAs RF IC we investigated could fail because of opens at R1 or shorts at C1 or C1.

Figure 2. A curve-tracer's display shows the current-vs.-voltage plot from tests on the RF input pin of the circuit shown in Figure 1. The positive and negative resistance changes indicate problems with internal components.
The first step in our analysis involved running a DC analysis on each failed IC to check for shorts or opens at the RF input terminal (Figure 1). The most direct path from the input to ground goes through resistor R1, but a short of either capacitor C1 or C2 would produce an alternate path to ground through the gate diode in FET Q1 or Q2. A short across C1 produces a decrease in the negative resistance (negative bend) at the RF input terminal, as seen by a curve tracer (Figure 2). On the other hand, a short across C2 produces a decrease in the positive resistance (positive bend). Of the nine failed parts, eight showed the signature of a C1 short and one showed the signature of a C2 short. That type of failure caused us to question the reliability of the capacitor dielectric.

Previous ESD characterization of the IC had shown that resistor R1 would likely fail at discharge levels below those that would damage either of the capacitors. Thus, it wasn't immediately obvious that an ESD event could damage a capacitor before it would damage a resistor in the circuit.

Locate the problem

After we "decapped" the eight ICs that indicated a short across C1, we used a liquid-crystal material to help locate the defects. (The liquid-crystal material changes its optical characteristics in response to temperature changes.) Because resistor R1 provided a low-resistance path to ground, the heat it produced made fault isolation difficult. We decided to destructively "remove" R1 from the circuit by applying enough voltage—about 2.5 V in this case—to the RF input to "open" R1.

After removing R1, we used the liquid-crystal material to locate any hot spots. Our analysis revealed a hot spot in C1 for all eight ICs, thus each failed capacitor contained a short. On one device we could observe a spot on capacitor C1 at the same location as the short we identified earlier (Figure 3). This spot looked similar to those seen on other capacitors known to have suffered ESD damage.

To determine whether the spot was a particle, a hole, or a bump, we had to "deprocess" the IC to get down to the top plate of the capacitor. We knew from experience that a plasma etch of the dielectric would leave unwanted residue, a reactive-ion etch (RIE) "grass" on the surface. So we developed a wet-etch method that left only a thin, clean layer of silicon nitride on top of the capacitor.

Because successive dielectric layers of silicon nitride and a low-k dielectric covered the capacitor, we could use the chemical characteristics of the low-k dielectric, along with a laser, to remove the  nitride layers.

Figure 3. A visible-light photo of a failed device shows a small spot revealed by liquid-crystal material. This hot spot indicates a short circuit.

Figure 4. An image from a scanning electron microscope (SEM) shows the trench etched around a defective capacitor by a laser. (The arrow points to the defects' location.)
Figure 5. (a) The bump on a defective GaAs RF IC, as seen in this SEM image, indicated the location of a short circuit. Compare the bump in (a) to the known ESD defect—also a short circuit—shown in (b).
Figure 6. The SEM image of a device tested using the CDM shows a bump similar to those in Figure 5 that indicate short circuits in capacitors.
We used the laser to cut a trench around the capacitor on a failed device (Figure 4) and performed the same procedure on the IC with the known ESD defect. After cutting the trench, we used sulfuric acid to preferentially etch the low-k dielectric, and we used a quick ultrasonic cleaning to lift away the detached nitride layers. We could then observe the top plate on each capacitor. After deprocessing, the failed IC showed a small bump (Figure 5) in the same location as the hot spot identified earlier. This bump appeared similar to the one observed on the deprocessed IC with the known ESD damage.

Because of the similarities, it seemed likely the damage to the nine ICs that failed during retest was due to ESD damage. To test this hypothesis, we devised an experiment to try to reproduce the failure mechanism. Previous ESD testing on the RF IC using the Human Body Model (HBM) and Machine Model (MM) always damaged resistor R1 rather than either capacitor C1 or C2 . So, we included the CDM along with the HBM and the MM in our series of ESD tests. (See "What's an ESD model?").

Test with three ESD models

For our experiment, we chose 45 known-good RF ICs—15 for each ESD model. The test result showed that HBM and MM consistently produced an open or a high resistance on the RF input. On the other hand, CDM yielded a positive or negative bend in the curve trace—the same type of response observed for the original nine test failures we investigated.

An internal visual inspection of the 45 tested ICs verified that testing with the HBM and the MM had overstressed the resistor, thus causing the high resistance. We deprocessed the 15 failed ICs produced during CDM testing and found the same shorted capacitors in each device (Figure 6) as we saw in the original nine retest failures.

Recall, though, that an overstressed resistor, the signature of an HBM or MM event, caused none of the failures seen on the test floor. Problems with the dielectric—our early suspicion—didn't cause problems, either. The nine original devices failed due to a shorted capacitor, the same failure mode found with CDM ESD testing. Thus, for us, the CDM ESD model represents the type of ESD event most likely to occur for a GaAs RF IC, or similar device, on the test floor. Our results underline the importance of testing and characterizing the CDM ESD performance of a device, as well as testing its HBM and MM characteristics. And they show the importance of not only finding a failure but also determining its cause.


Author Information
Amy Poe worked at TriQuint Semiconductor for two and a half years as a failure-analysis engineer before leaving to join a family business. She has a master's degree in physics from Oregon State University.
Steve Brockett has been with TriQuint for six years and is now the customer returns and failure-analysis manager. He has a BS in physics from Oregon State University, and he worked at Intel and Lattice before joining TriQuint.
Tony Rubalcava has worked as a reliability engineer at TriQuint for most of his 18 years with the company. He is now a failure-analysis engineer at TriQuint.


Acknowledgement
Information contained in this article was included in "Failure Analysis of CMD ESD Damage in a GaAs RFIC," ISTFA 2000: International Symposium for Testing and Failure Analysis, ASM International, Materials Park, OH. November 2000. Used with permission.

 

What's an ESD model?

The electronic industry uses three standard models to simulate ESD events: the Human Body Model, the Machine Model, and the Charged Device Model. Figure A shows schematic diagrams for the circuit used by each model (Ref. 1, 2, and 3).

The Human Body Model (HBM) is the oldest and most widely recognized ESD model. It was developed at a time when most ESD damage occurred as people touched parts without proper grounding. The capacitance and impedance of the human body vary widely, so the component values in the model were arbitrarily set to facilitate comparative testing. Devices damaged by HBM ESD generally have thermally damaged junctions, melted metal lines, or other types of damage caused by a high peak current and a high charge dissipated over several hundred nanoseconds. This model still applies whenever people handle devices, so you should perform HBM testing on all new device designs.

The Machine Model (MM) finds use primarily in Japan and Europe. The MM was developed originally as a "worst-case" HBM to duplicate the type of failures caused by automated pick-and-place machines used to assemble PCBs. The model simulates a low-impedance machine that discharges a moderately high capacitance (200 pF) through a device. A discharge produced using the MM can cause damage at relatively low voltages.

The Charged Device Model (CDM) reproduces realistic ESD damage that occurs in small, plastic-packaged devices. As a packaged device slides on a surface, it accumulates charge due to triboelectric (friction) action between the plastic body and the surface. Thus, the device picks up a charge that produces a potential. (In the HBM and the MM, something external to the device accumulates the charge.) For small devices, the potential can be surprisingly high. Potentials of at least 650 V are needed to duplicate the observed damage.

When you simulate an ESD event using the CDM, you charge the device to a fixed potential and then discharge it. As a result, the tests often require higher voltages to cause failures than do tests that use the HBM. The popularity of CDM testing has increased as companies realize the importance of protecting circuits against damage from ESD that occurs on production lines. The JEDEC committee JC14.3 is now revising the JEDEC "Stress-Test Driven Qualification of Integrated Circuits" spec (JESD47) to require CDM instead of MM testing.—Steve Brockett

References
  1. EIA/JESD22-A114-B: "Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM)," EIA/JEDEC Standard, June 2000. www.jedec.org
  2. EIA/JESD22-A115-A: "Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM)," EIA/JEDEC Standard, October 1997. www.jedec.org
  3. JESD22-C101-A: "Field-Induced Charged-Device Model Test Method for Electrostatic Discharge Withstand Thresholds of Microelectronic Components," JEDEC Standard, June 2000. www.jedec.org
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