Logic Analyzers: Digital Detectives

When you need to track a multitude of signals, put a logic analyzer on the case.

Martin Rowe, Senior Technical Editor -- Test & Measurement World, 1/1/2001

You’ve been there many times, trying to use a scope to simultaneously look at many signals on a digital bus. Scopes are great for viewing a signal’s details, but most can handle just two or four channels, making it difficult—if not impossible—for you to view signals on even an 8-bit bus. If you need to look at signals across address and data buses, and don’t need to see the signals’ vertical details, you need a logic analyzer.

What does a logic analyzer do? A logic analyzer captures dozens or even hundreds of digital signals, each with 1-bit resolution—displayed signals are either high or low. Some bench logic analyzers offer both multiple 1-bit logic channels and two 8-bit DSO channels. And a logic analyzer processes data across buses—something a scope can’t do.

The key to using a logic analyzer is to configure it properly. You’ll need to choose an analysis mode, connect the analyzer to the signal leads, and set up triggers. Once your setup is complete, you’ll be ready to track down hardware and software bugs.

Choose time or state

Logic analyzers operate as either timing analyzers or as state analyzers. The timing analysis mode lets you view digital signals as waveforms, which lets you see the timing relationships among signals. Figure 1 shows digital waveforms, a trigger condition based on pulse width, and a trigger marker (on the far right of the image).

Logic analyzers supply you with more information than you can view on a screen, or than your eyes and brain can process. But instrument makers have supplied various means for simplifying displays, such as letting you name signals, name buses, and color-code leads. Especially important is the logic analyzer’s ability to combine signals into groups (or buses).

Figure 1 shows three buses named “4-bit-counter,” “8-bit ADC,” and “IO port.” When a logic analyzer combines signals in a bus, it also gives you the “value” on the bus in binary, decimal, or hexadecimal format. Thus, the screen shows the hex values of the 4-bit counter and the 8-bit ADC, while it shows the individual signals for the I/O port bus.

When you use a logic analyzer in timing-analysis mode, the instrument’s internal clock controls the sample rate. Timing mode is sometimes called asynchronous mode because the logic analyzer’s sampling isn’t synchronized to anything in the target system.

How do you decide what clock frequency to use? According to Nicholas Rexing, product manager at Tektronix (Beaverton, OR), you should set a logic analyzer’s clock frequency so the time between clock pulses is five times faster than the shortest timing change you want to accurately measure.

By capturing waveforms, you can see the timing relationships among digital signals, but remember, those signals represent data. When debugging software, you usually need to view the data that the signals represent rather than the signals themselves. That’s where state analysis comes in.

Figure 1 Logic analyzers display waveforms of individual signals and data values of signal groups, or buses. Courtesy of Agilent Technologies.

Unlike timing analysis—where the logic analyzer provides the sample clock—state analysis requires you to provide the sample clock. Engineers often call state analysis synchronous mode, because the analyzer’s sampling is synchronized to an external clock. In many applications, you’ll want to use a target system’s clock as the logic analyzer’s sample clock. If you need to see activity between clock pulses, use an external clock source such as a function generator to clock the logic analyzer.

Figure 2 In state mode, logic analyzers display data values as signal lines move through their activities. Courtesy of NCI .

Regardless of whether you need to view signal waveforms or their numerical equivalents, you won’t get valid information unless your instrument properly captures data. The most common method of probing a target system involves connecting individual leads to the target. Connecting these leads, called “flying leads,” to circuits is often difficult because of tight PCB spaces and fine-pitch IC lead pins. If you’re working at the development or prototyping stage and board space and signal integrity allows, design a system with male headers that will let you connect a ribbon cable to your logic analyzer. It’s a lot easier to make all connections at the same time than to connect individual leads. If there’s no PCB real estate available for a ribbon cable, you can use an adapter to make your processor’s pins accessible (Ref. 1).

If you use flying leads, remember that capacitance in signal leads can degrade signals to the point where your logic analyzer can’t detect them. Capacitance in the leads loads a board’s signals, reducing them to below a logic analyzer’s detection threshold. You can minimize lead capacitance through proper grounding.

Steve Warntjes, product manager at Agilent Technologies (Colorado Springs, CO), says engineers too often connect just one ground lead to the logic analyzer when probing a 16-channel bus. Warntjes recommends that you connect as many ground leads as possible to your target system. Try to use one ground lead per signal and connect to ground as close as possible to the corresponding signal leads.

Connecting dozens of flying leads to a board can get hairy, so be sure to record where you connect each flying lead—some logic analyzer manufacturers supply color-coded leads or clips. Most logic analyzers also let you assign meaningful names to each signal and each bus. You can easily spend more time tracing leads over and over again than you’d spend assigning helpful names such as INT-3 or OUT5 to traces when you first set up your instrument.

Engineers have different philosophies about connecting signals. Which approach you should take often changes as a design project moves toward completion. If you have a mature design that has only one specific problem, you might start by connecting only those signals you think you’ll need to view to solve the problem. As a rule of thumb, use only 12 to 14 signals in a given 16-bit probe. You can add more signals without rebuilding the entire setup, and you’ll save time by not connecting unnecessary signals.

If your design is new or unproven, however, then consider connecting many of the address bus, data bus, and control lines right at the start. With most of the logic-analyzer channels lines attached to the target system, you should have access to enough data to solve even complex problems.

Set up your trigger

Once you attach your target system to a logic analyzer, you must configure the instrument to get the data you want. Inevitably, you’ll have to set up one or more triggers.

The relationship between a logic analyzer’s triggers and its memory is functionally the same as that in a DSO. The instrument detects one condition, a set of conditions, or a sequence of conditions. A logic analyzer places a marker in its memory whenever it detects the condition, and then it continues to fill the memory (Ref. 2). The instrument indicates the trigger point on its display.

Just like a DSO, a logic analyzer can display data both before and after the trigger event. Unlike a DSO, though, a logic analyzer’s default operation is single-shot acquisition as opposed to repetitive sampling.

Triggers come in many shapes and sizes, ranging from a simple edge detection on a single channel to a pattern or range of patterns across many channels. With a basic trigger, you simply select a pattern of 1’s and 0’s on a channel or a bus, perhaps when an ADC output port holds the value 11111110. You can also set a logic analyzer to trigger within a range of patterns. Suppose you have a PCI card that requires four addresses. You can set the logic analyzer to trigger whenever it “sees” any address within the range of interest.

You also can set the instrument to trigger on a rising edge or a falling edge. And you can combine patterns and edges to specify a specific event, such as the value of an address bus coincident with a falling edge on an address strobe line.

A pulse’s duration also can trigger a data capture. Suppose an error occurs when a VXIbus card writes to the system bus with too short an address-valid pulse. In this case, you would trigger the analyzer each time the VXIbus card writes data to the system bus and an address-valid pulse occurs that’s less than n nanoseconds wide. You could set the logic analyzer to trigger whenever the VXIbus card enables its address-valid pulse and then add the pulse-width constraint to the trigger setup.

Trigger conditions can include the results from event counters and timers. Event counters help when you need to trigger a data capture after an event occurs n times. If your hardware writes to the same address to increment a 4-bit counter, for example, you may be interested in the target system’s behavior when the counter overflows. In this case, set the logic analyzer to trigger on a value of 00 hex (for a 4-bit counter) when overflow occurs.

Timers set a logic analyzer to look for specific events within a time window of other events. The most common use of trigger timers is to measure setup-and-hold time on address or data buses. Say you have a problem only when a data-valid signal occurs more than 100 ns after an address-valid strobe activates. Using a timer, you can set the logic analyzer to look for an address-valid strobe, wait 100 ns, and then look for a data-valid signal. In this case, you’ll capture signal states when the problem occurs, but not the states in which the circuit works properly.

Figure 3 You can gradually build a trigger sequence from simple events. Courtesy of NCI .

Logic analyzers let you set up triggers with two or more levels or sequences. These sequences let you set a condition, test that it occurs, and only then go on to another condition, repeating the process until you build a series of conditions that let you isolate the trouble. Think of these sequences: “Trigger the analyzer should condition A occur, followed by condition B occurring 27 times but only if condition C occurs within some period of time after one of the B occurrences.” Figure 3 demonstrates how you might set up a trigger sequence using two trigger levels. As you can see, this analyzer lets you go eight levels deep.

When might you want to use a multilevel trigger? You might need to trigger an acquisition when a system writes the wrong data to an I/O port. Start by setting the analyzer to trigger whenever the target system writes data to the port’s address. That may not be enough, though, and you may need a two-level trigger. Your trigger might activate only on a specific pattern on the data bus following a write to the I/O port.

Building a qualified trigger often takes place in increments. You should start with a single trigger condition and add conditions and sequences as needed. Assigning meaningful names to patterns and events helps avoid confusion as you build a complex trigger. You can also document your triggers by drawing flowcharts as you go. Documenting your triggers can help you avoid trying the same thing twice. Also, don’t forget to save those trigger setups as files, because you may find that you need to go back to a previous setup and build upon it.

With their ability to provide views across buses and with their data-processing tools designed for digital troubleshooting, logic analyzers shouldn’t be relegated to the top shelf of your test lab. Given the chance, these instruments will give you insight into a system’s operations. T&MW

References

1. Shipke, Brian, “Design Embedded Systems for Probing,” Test & Measurement World, November 1997. p. 55.

2. Nelson, Rick “Logic Instruments Tackle Troubleshooting,” Test & Measurement World , April 2000. p. 51. 

For more information

For up-to-date information about companies, visit the Stand-Alone Test Instruments portion of our Buyer's Guide.

Application note 1326: 8 Hints for Solving Common Debugging Problems, Agilent Technologies, Santa Clara, CA, publication number 5968-5700E, May 2000.

Strassberg, Dan, “Don’t be illogical when choosing logic-analysis tools,” EDN, March 18, 1999. www.ednmag.com. 

Martin Rowe has a BSEE from Worcester Polytechnic Institute and an MBA from Bentley College. Before joining T&MW in 1992, he worked for 12 years as a design engineer for manufacturers of semiconductor process equipment and as an applications engineer for manufacturers of measurement and control equipment. E-mail: m.rowe@tmworld.com.