Multisite test cuts time and costs

You can adapt your ATE to perform multisite tests, but you'll have to ensure adequate correlation among sites.

Tony Zizzo, Jr., and Saeid Jannesari, Texas Instruments, Tucson, AZ -- Test & Measurement World, 6/1/2001

Multisite testing is evolving from a novelty to a necessity as business requirements force test engineers to get the greatest return on their ATE investment. Multisite tests can reduce the average testing times per DUT in almost any device-test application, increasing throughput and saving money. As you develop multisite systems, though, you must contend with several core design issues. You can see whether using a multisite tester will help you by performing a few calculations.

Total test time consists of several components: the time a test system spends applying electrical tests (T_test), the time a handler spends sorting tested components into bins (T _sort), and the time a handler spends inserting DUTs into and removing them from the test board (T_handler ). The total time between test starts—test time plus handler time—is the index time.

You’ll generally get the highest throughput improvements from multisite testing if you can apply redundant instrumentation to each site. But even if you can’t do that, you’ll still realize time savings if you apply a single set of instruments sequentially to each site. A multisite IC handler normally inserts devices into all sites and then sorts and bins parts from each site while the ATE system performs electrical test on another set of parts. Therefore, the sort time is hidden within test time if test time is greater than sort time. For such a case, the total equivalent test time per part (T_device) for an N-site test is

T_device = T_test + T_handler/N                             (1)
for T_test  ³ T_sort

Of course, IC handlers have limits, and test times can be less than sort times. In that case, devices remain inserted after completion of electrical tests until the handler finishes sorting and binning the previous set of devices. In this case, test time is approximately

T_device = T_sort(N)                                           (2)
for T_test £ T_sort

Sort times are on the order of 1s, so it’s unusual for sort times to exceed test times.

Now, consider the best case for electrical test time. If your tester duplicates at each site all the resources—instruments, communications channels, and processing capability—required to test a DUT, then the multisite device-test time approaches

T_device = (T_test + T_handler)/N                           (3)
for T_test ³ T_sort

It is apparent from Equations 1 and 3 that

T_test/N £ T_device – T_handler £ T_test                (4)
for T_test ³ T_sort

Handler time depends solely on the handler you employ; you cannot improve the time after you’ve made your handler selection. Electrical test time, though, is something you can shorten by employing good test-engineering practices. Some test-system qualities related to resource availability affect the overall test time:

• instrument availability,
• instrument performance,
• instrument execution time,
• data read time, and
• data-processing time.

One of the most important decisions you must make is whether to use parallel or serial test: For each subtest, you must determine whether to test multiple test sites sequentially or simultaneously. Ultimately, you might perform some subtests serially and others in parallel.

Instrument performance

If for an N -site test, N resources are not available for a particular subtest, you’ll have to make tradeoffs: You could add more instruments, of course, but costs may make this choice unattractive. Before doubling up on instruments, consider whether substituting a single, slightly more expensive instrument would suffice.

For example, suppose you can choose one high-resolution meter or four low-resolution meters to serve four DUT sites. Using the lower resolution meters, you’ll need to acquire more data points to get the same accuracy that the higher resolution meter would provide, translating into increased measurement and processing times. You’ll need to look in detail at what’s required of each instrument to get the required performance—then you can see which is faster.

Unless your test system has a coprocessor or digital signal processor, it will compute results serially. Some serial systems can process results from one subtest or one site while system instruments obtain results of the next subtest or site. Depending on the instrument execution time and instrument read time for each pair of consecutive subtests, you may save time by serializing instrument operations so site 1 results are processed while site 2 data is acquired. If processing times are long with respect to measurement times, you might find you can—without exacting a time penalty—have one instrument make sequential measurements rather than use multiple instruments to make simultaneous measurements.

Figure 1. (a) You can employ multiplexing to reduce DUT tester-pin requirements for DUT outputs that needn’t be measured simultaneously. (b) In addition, you might be able to derive a stimulus signal (a sampling clock, for instance) from a closely related one (a data clock, for instance).

Resource allocation

Obviously, the number of digital tester pins available vs. the number of DUT pins determines whether you can employ multisite testing for a particular DUT on a particular tester, but simple integer division might not tell the whole story. For example, suppose you’re testing a 48-pin thin quad flat pack (TQFP) package that requires 36 dedicated digital pins. If your tester provides only 64 digital pins, multisite testing would seem precluded. Sometimes, however, you can employ techniques such as multiplexing and derivation (Figure 1) to cut down on the number of test pins a DUT requires. For source instruments, you can typically employ a splitter or buffer that enables the source to simultaneously apply an isolated stimulus to each site. If the instrument is a meter, you can often employ a multiplexer to enable the instrument to make sequential, yet rapid, measurements at each site.

Whether or not your multisite tester has multiple processors, you can probably program it to mimic parallel processing. With parallel processing, instruments can simultaneously send new data collected from multiple sites to memory while the tester processor performs serial computations. To take advantage of this parallel-processing technique, the total processing time for all sites, T_P (N), should be less than or equal to the simultaneous data capture time, T_C:

N(T_P) £ T_C                                      (5)

Modern mixed-signal ATE comes with many very fast signal-processing algorithms. To minimize processing times, choose algorithms appropriate for your application. For example, you might consider using a linear convolution algorithm to implement a finite impulse response (FIR) filter on the outputs of a sigma-delta modulator.

If the calculation involves a large number of samples, though, you might find it more efficient to employ a fast Fourier transform (FFT) algorithm to perform the convolution. If Equation 5 holds true, you can reduce total test time if you can capture less data and perform more processing—with equivalent results. Otherwise, you can attempt to capture more data if that would reduce processing demands.

For any production-test application, you’ll need to perform intensive guardbanding analysis to ensure your product ships within spec. Guardbanding analysis takes place during what we call the capability/correlation phase of test development; the capability/correlation phase involves measuring the capability of the test system to measure a particular parameter to a specified accuracy as well as the ability to correlate to previous measurements (precision). The goal for a multisite system is to ensure test limits are set so that a passing part is guaranteed to meet spec no matter which site provided the test and to provide minimum guardbands to maximize yield.

Thorough guardbanding analysis often uncovers subtle but consequential flaws in the test, particularly in high-performance products that push the performance limits of the tester. Guardbanding analysis can increase development time (Figure 2), but that’s time well spent, because in a multisite system, site-specific errors can have far-reaching consequences. A test design that provides good single-site performance can, when duplicated, exhibit large site-to-site variance (or poor site-to-site correlation), resulting in yield loss. (We are assuming that one set of limits applies to all sites—site-specific limits are unusual.)

Figure 2. You must account for site-to-site variances during the capability/correlation stage of your multisite test development.

Site-to-site variance can occur for many reasons. First, site performance is layout dependent. Because test resources are located around the perimeter of the test board, you can seldom duplicate one site’s layout at other sites. Line lengths will be longer for some sites, and some sites will be located closer to interference sources. You must take these factors into account during test development.

Speed and accuracy tradeoffs

As always, speed and accuracy (plus precision) are at odds. Steps taken to enhance capability/correlation results by increasing accuracy and precision usually cause unwanted increases in test time. Conversely, speeding up test almost always results in poor capability/correlation. Resource allocation, layout, component choice, and program design all play a role in the test-time vs. capability picture.

The following example illustrates the impact of multiple sites on capability. Suppose you have two test solutions for the same product on the same test system. In one, you have N single-site test boards, and for the other, you have one N-site test board. We know that the test uncertainty for either solution is

             (6)

where

s_m is the standard deviation of a single DUT (the mth unit) measured once in each site for the multisite approach or once on each board in the single-site approach,
M is the number of DUTs used to study the test-system uncertainty, and
c₄ is the bias correction factor dependent on N.

The multisite solution will have greater uncertainty than the single-site solution, and you can be certain it won’t be better—because of the layout, resource-allocation, and test-design issues. In some multisite systems, site uncertainty may vary depending on events occurring in another site (resulting in crosstalk).

Because in the multisite solution there may be resource multiplexing and test delays pending the completion of serial processing, DUTs in some sites may experience deviation based on thermal settling in nonactive sites. In other words, the DUT in one site experiences a brief cooling period while DUTs in other sites are being tested—resulting in unequal device test temperatures across sites. You can minimize the impact of multiple test-circuit instances on capability/correlation by paying careful attention to layout and component selection and to careful program design.

Layout and components

Good circuit design and layout is important to any test solution and it’s critical for multisite mixed-signal test development. Good layout techniques are essential for achieving the good site-to-site matching required to prevent unnecessary yield loss and to isolate each test site from interference from its neighbors. For mixed-signal devices, much of the test is dedicated to testing digital circuitry at very high speeds; therefore, signal-integrity issues play an important part in the design and layout of the test board. If line-length and line-location differences among sites contribute to different levels of cross coupling and ground bounce, correlation will suffer.

You generally don’t want to split the ground plane when designing high-speed circuits with fast switching outputs. You needn’t do so with multisite test boards, either, but you will want to run separate analog and digital power-supply lines to each site. Be careful to separate noisy digital ground returns from sensitive analog ones to minimize coupling of switching transients to the DUT through power and ground lines. Isolate the sites as much as possible, and never route a signal line for one site through another site. Ultimately, part placement and signal routing are more important than whether you split ground planes.

When balancing circuit-performance and site-matching considerations, you must select the right kinds of passive, active, and electromechanical components. Use close-tolerance passive components, and choose active components with site-matching as well as performance in mind. For example, an op amp used to buffer a high-frequency stimulus to each site should have not only the appropriate bandwidth and slew rate but also distortion and offset properties that won’t degrade your multisite matching.

Follow these suggestions for digital components:

•  Make sure digital components can drive high-capacitance pin instruments.

•  Do not use the DUT supply to power your digital components, even if it’s the digital supply of a mixed-signal tester.

•  Always decouple the power supply at the digital component. Use a 10-µF polarized capacitor in parallel with a 0.1-µF chip capacitor. (If you group two or three digital components close together, they can share a single 10-µF polarized capacitor.)

For relays, you can choose among conventional or latching electromechanical versions or solid-state CMOS versions. Latching relays offer the best performance: Like conventional relays, they exhibit minimal contact impedance and parasitic capacitance, and they offer low insertion loss into the gigahertz frequency range. But unlike conventional relays, latching relays offer low thermal EMF across their contacts, because heat-producing relay coils are activated only momentarily during switching. They do, however, require two drivers.

CMOS relays operate at high speeds, don’t have high drive-current requirements, and include no moving parts, enhancing their reliability. They do, however, exhibit several drawbacks that can make them unsuitable for multisite test systems. They provide voltage-dependent on-resistances of 10 to 100 W, vs. 0.5 W or less for electromechanical relays. They also have high gate capacitances that tend to limit bandwidth. Consequently, they are best reserved for low-frequency, low-current applications.

Impedance matching

As digital-circuit switching rates increase, PCB traces begin to look like transmission lines. For your digital circuits, you’ll need to provide terminations that match trace characteristic impedance to maintain signal integrity and minimize reflection, crosstalk, and ground bounce. Serial terminations (at the source end of a signal) are generally preferable to parallel terminations (at the load side) because of power-dissipation considerations. You can use this equation to calculate a trace’s characteristic impedance:

    (7)

where
e_r = PCB relative dielectric constant
T = trace thickness
W = trace width
H = height of trace above ground plane.

The PCB relative dielectric constant depends on PCB material and generally lies between 3.8 and 4.2—you’ll have little control over this parameter. Trace thickness, too, offers you little control; you can’t reduce it beyond about 1 mil without compromising quality. You’ll want to keep trace width as wide as possible; reduced widths will increase impedance, resulting in higher crosstalk. Unfortunately, multisite test boards require dense component placement, making it difficult to accommodate wide trace widths. Yet, taking time to improve impedance matching will be worth it, as proper terminations reduce interference between adjacent traces and sites on a multisite board.

Ultimately, the additional effort you expend to implement multisite tests will pay off. Companies measure test costs in cents per second, and the time savings derived from an effective multisite test strategy translate directly to cost savings. T&MW

For more information

Mazza, Ed, “Asynchronous Testing Increases Throughput,” Test & Measurement World , December 2000. 

Zizzo, Tony, Jr., “Technique Closes the Loop on Test System Uncertainty,” Test & Measurement World, May 1999. p. 39. 

Tony Zizzo Jr. and Saeid Jannesari are test engineers at Texas Instruments, Tucson, AZ.

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