Special tests bracket device life cycle

Wafer-level tests help get designs and processes working and enable device repair, while tests of disassembled packages can pinpoint timing problems.

Rick Nelson, Senior Technical Editor -- Test & Measurement World, 7/1/2001

During manufacturing test, structural and functional testers maximize throughput while ensuring that products offer adequate quality levels (Ref. 1). Throughout device life cycles, however, other test systems are brought into play to qualify devices.

During production test, structural testers can provide graded test patterns to initiate scan test or to activate built-in self-test (BIST) functions; they subsequently monitor device response to determine DUT structural integrity. Meanwhile, functional testers can mimic real-world device inputs and measure outputs for some subset of inputs the DUT would see during operation. Both types can be configured to test either packages or wafers, depending on the handling and probing systems with which they are coupled.

The success of such tests, however, is predicated on the existence of a proven design implemented in a proven silicon process. Standard structural and functional testers are limited in their abilities to pinpoint why particular DUTs fail and to effect repairs. To that end, systems are available that can make the precise measurements to fine-tune designs, that can identify bad silicon segments requiring repair on certain devices, and that can help determine why certain DUTs fail. These systems range from parametric test systems that measure very low currents at the wafer level to systems that visually monitor signal propagation on chip-scale packages.

Parametric tests

Figure 1. Designed to characterize copper interconnects having line widths of 0.13 µm and less, Keithley’s S633 Series DC parametric test system can handle 300-mm wafers.

Parametric testers and semiconductor characterization systems from firms such as Agilent Technologies and Keithley Instruments can help to get complex new designs up and running in submicron silicon processes. For example, Keithley’s Model S633 parametric tester (Figure 1) is designed to characterize copper interconnects having line widths of 0.13 mm and smaller. To evaluate the low-k dielectric materials required for such designs, the S633 can make femtofarad-level capacitance measurements.

When making such low-level measurements, you’ll need to minimize noise sources. Keithley makes recommendations relating to grounding, shielding, instrument noise, and thermal noise (Ref. 2). Those recommendations include separating noisy power grounds from measurement common ground, eliminating ground loops (by, for example, plugging all instrument and probe-station components into the same outlet), and using DC instead of AC heaters for thermal chucks.

Agilent Technologies lists several factors that can contribute to low-level measurement errors (Ref. 3):

• ionic contamination of probe cards or personality boards, which can degrade insulation resistance or establish conductive paths to ground;

• humidity, which can cause condensation that can also establish conductive paths to ground;

• light, which when hitting a semiconductor can generate electron-hole pairs that generate currents that interfere with accurate low-current measurements;

• triboelectric cable noise, which results from friction between a conductor and insulator;

• piezoelectric cable noise, which results from mechanical deformation applied to insulation;

• power-line noise, which can degrade measurements when the large surface area of a prober chuck acts as an antenna; and

• dielectric absorption effects, which arise in response to a varying electric field or which can appear when electric fields remain constant but when capacitances change in response to mechanical vibration.

Minimizing noise therefore requires that parametric test equipment be adequately shielded from electromagnetic noise and light, that cable lengths be kept short, that chucks be properly shielded and grounded, and that mechanical integrity be maintained to minimize vibration. With noise sources adequately controlled, Agilent’s 4070 Series parametric testers (Figure 2) can measure 500-fA levels averaged over 16 power-line cycles.

At the parametric-test stage, throughput is not the major issue it is at production test, where an extra second or two of test time can make an otherwise successful product a financial failure. Nevertheless, it’s never a good idea to waste time, so it can be beneficial to automate parametric tests as much as possible; just as production test aims to minimize the number of test-socket insertions, during parametric test you should minimize the number of separate required probing operations. To that end, you can use an instrument switching system to connect multiple instruments to a single probing system. For example, one instrument might make current and voltage measurements on one test-element group (transistor circuits added, often within wafer score lines, for test purposes) while another instrument might make the capacitance measurements on another test-element group required to verify proper dielectric thickness in a wafer (Ref. 4).

Wafer test in production

Parametric test systems find most use during product ramp up, but wafer-level tests remain important even in high-volume production. Semiconductor manufacturers want to detect defects as early as possible. If wafer-level tests indicate a process flaw that is depressing yields, the problem can be corrected promptly. If the flaws don’t emerge until package test, then too much effort has gone into singulating and packaging bad dice and the production of bad wafers has continued for an unnecessarily long period. Many semiconductor production test systems can be configured to perform wafer-level tests. Some, however, are tailored for the task.

Figure 3. Aimed at wafer-level tests of DRAM devices, Teradyne’s Probe-One isn’t restricted by JEDEC-defined pinouts.

For example, Teradyne’s Probe-One memory test system (Figure 3) supports the parallel test and repair of DRAM wafers. The company notes that for package test, pin counts are fixed by JEDEC specifications, and parallel test capabilities are limited by handler restrictions. In wafer test, however, parallelism is limited only by the tester and probe-card configuration. In fact, the number of pads per die can vary, and die boundaries are flexible. Teradyne has worked with FormFactor to help characterize probe performance (Ref. 5); Probe-One works with probe cards from FormFactor as well as other manufacturers. The system is designed to identify bad memory cells, replacing them with redundant ones embedded in the silicon.

Wafer test is an invaluable step leading to final test of packaged devices in production. For a packaged device that fails to operate properly, however, manufacturing test cannot shed much light on exactly what portions of the device failed. To handle such chores, systems such as laser and e-beam probers can peer into bad devices in an attempt to locate defective structures. The newest twist is a system that actually observes transistor operation, allowing you to follow, for example, clock signal propagation throughout a chip (Figure 4).

Figure 4. Photon emissions from switching transistors power Schlumberger’s IDS PICA system. Shown here is a single frame of a movie you can view at IBM’s Web site (see Ref. 7). Courtesy of IBM.

Seeing the light

Called PICA (picosecond imaging circuit analysis), the technique, invented by IBM scientists (Ref. 6) and commercialized by Schlumberger as the IDS PICA, relies on observing the photons emitted when MOS transistors switch (Ref. 7). It involves dissecting a package and polishing substrate surfaces to permit light transmission to an observing camera.

The technique is not fast—it has a million-to-one chance of capturing a photon when a particular transistor switches, and it needs about 100 photons for a detectable measurement—so it requires a DUT be placed in a looping operation for many hundreds of millions of cycles. Given sufficient time, however, it measures signal propagation with 10-ps accuracy, with the system’s camera set to acquire images at successive timing intervals, much as does a sampling oscilloscope.

As the PICA system measures light emitted by a DUT, it doesn’t affect DUT performance, as laser probing can. Schlumberger’s commercialized version is now qualified for 0.13-mm processes and, being scalable without the wavelength dependencies of active probing systems, will go lower. T&MW

References

1. Nelson, Rick, “DFT lets ATE work magic,” Test & Measurement World, May 2001, p. 16.

2. “Making Ultra-Low Current Measurements with the Low-Noise Model 4200-SCS Semiconductor Characterization System,” Application Note 2241, Keithley Instruments, 2000.

3. “Ultra Low Current DC Characterization at the Wafer Level,” Application Note 4070-1, Agilent Technologies, 2000.

4. “Accurate and Efficient C-V Measurements,” Application Note E5250A-3, Agilent Technologies, 2000.

5. “A New Wafer Probe Interface Technology Using Compliant Microsprings,” Joint study by Teradyne and FormFactor.

6. Knebel, Dan, et. al., “Diagnosis and Characterization of Timing-Related Defects by Time-Dependent Light Emission,” Proceedings, IEEE International Test Conference 1998.

7. For movies showing PICA in operation, see www.research.ibm.com/topics/popups/serious/chip/html/pica.html.

Rick Nelson received a BSEE degree from Penn State University. He has six years experience designing electronic industrial-control systems. A member of the IEEE, he has served as the managing editor of EDN, and he became a senior technical editor at T&MW in 1998. E-mail: rnelson@tmworld.com.