Systems Expand IEEE 1149.1 Test

Dedicated boundary-scan controller hardware systems and in-circuit ATE deliver test vectors to PCBs under test in the production environment.

Rick Nelson, Senior Technical Editor -- Test & Measurement World, 2/1/2000

A previous article looked at software that can synthesize boundary-scan circuitry within ASICs and that can generate test patterns for boundary-scan-enabled testers (“Boundary-Scan Software Aids PCB Evaluation,” Test & Measurement World, October 1999, p. 65). Using such tools, you can derive a boundary-scan-description language (BSDL) representation of your design as well as generate test-vector sets. When it’s time to actually test some boards on the production floor, you’ll need to roll up your sleeves and work with the hardware that applies the test-vector sets to your units under test.

Dedicated Controllers

Such hardware brings to mind the dedicated boundary-scan controllers from specialized firms like JTAG Technologies, eponymously named for the Joint Test Action Group, an ad hoc group that pushed boundary scan forward toward IEEE standardization. Yet boundary-scan capability also appears in general-purpose in-circuit testers and flying probers from traditional ATE suppliers. You can choose from a variety of boundary-scan harware configurations. 

The IEEE boundary-scan standard—designated 1149.1—defines the four-wire Test Access Port (TAP), which includes a test-mode-select (TMS) signal, a test-clock (TCK) signal, and a test-data-input (TDI) and a test-data-output (TDO) signal. With the TMS pin asserted, a boundary-scan controller clocks serial test data through a UUT’s TDI and TDO pins at rates to 25 MHz.

In boundary scan’s simplest form, successful circulation of test data patterns through the UUT indicates continuity through all scan-enabled IC pins that make up the UUT’s scan chain—a group of series-connected TDIs and TDOs. In other words, basic boundary scan merely determines whether boundary-scan parts are soldered to your PCB. You can adopt more complex forms of boundary scan by designing into your UUT registers that can accumulate boundary-scan test data. After accumulating this data, the UUT manipulates it in response to commands embedded in the serial patterns arriving from the boundary-scan controller. The accumulated data can provide parallel stimuli to circuitry under test, whose responses can in turn be accumulated and shipped out over the TAP or measured by other test equipment at UUT test points.

Figure 1. Easy-to-use chip-design software packages are helping to ensure that boundary-scan components are readily available for populating dense multilayer PCBs. Additional software derives test-patterns from chip and board design data. You can use a dedicated boundary-scan controller, an in-circuit tester, or a flying prober to apply these test patterns to a board under test.

For example, a controller can signal that accumulated data be sent to non-boundary-scan-compatible components. If your board contains a 16-bit DAC, for instance, you could assign a boundary-scan register to accumulate a 16-bit word, then program your controller to enable latches that would transmit that word to the DAC input. Then you simply employ the appropriate analog instrumentation to measure the DAC output at the PCB edge connector or at a test point. For flash-memory and programmable-logic devices, the scan chain supplies programming data.

Unlike an in-circuit tester, whose bed of nails can probe any accessible PCB nodes, a boundary-scan controller typically connects to a board through an edge connector or dedicated four-wire TAP on the board conveniently accessible to a test technician. That makes sense. After all, the rationale for boundary scan is that multilayer PCBs densely packed with ball-grid arrays simply don’t admit to adequate bed-of-nails coverage—hence the need for boundary scan’s “virtual nails” that can plunge deep within buried layers and even deep within individual components on that board. In this scenario, you use boundary scan to look for basic device functionality and PCB solder defects; you can send boards that pass boundary-scan tests directly to final functional test, or even combine boundary-scan and functional tests within a single test station.

In-Circuit ATE Keeps a Role

Many factors can contribute to the length of time your UUT must be connected to your boundary-scan hardware. For example, you might choose to use a boundary-scan tool to program flash memory or programmable-logic devices in a single-pass device-programming/ boundary-scan-test operation. There are many good reasons to do this.¹ Nevertheless, such an approach will dramatically lengthen total test times because of the time required for the controller to pump serial data into the UUT’s programmable devices.

So don’t throw out your in-circuit tester yet. Even though PCBs exhibit ever more physically inaccessible nodes, a real bed of nails can still make many more contacts than are available over an edge connector, and those many contacts can be indispensable to ensuring that test times don’t become unendurably long. After all, the TAP remains a serial, one-bit-at-a-time interface; a bed of nails provides simultaneous, parallel access to many nodes, enabling you to simultaneously program onboard devices while testing boundary-scan components.

When estimating production-test throughput (including device-programming speeds, if applicable) during the PCB design stage, you should realize that your production boundary-scan test equipment is unlikely to achieve the TAP’s maximum 25-MHz rate. Your test hardware itself might not be able to keep up, the devices on the board under test might not meet the 25-MHz spec, or your board’s layout might not be able to handle 25-MHz I/O. You can address device-speed and board-layout limitations at the product-design stage by specifying fast parts and observing high-speed transmission-line design rules. That approach won’t be cost effective, however, if your board won’t see 25-MHz operation after leaving your factory. Also, you can employ data-compression schemes to help speed the flow of programming data into your UUT. Nevertheless, sending many megabytes worth of programming data over a single TAP can become a real bottleneck.

For their part, vendors of boundary-scan hardware are striving to improve achievable scan-chain data throughputs. One difficulty in achieving full speeds is the path delay you incur if you must use long wires to connect a boundary-scan tester to a device under test—a requirement you might face if using equipment such as a flying prober to deliver your test signals. Several meters of wire can contribute path delays approaching the 40-ns period of an ideal 25-MHz scan signal, so TDI and TDO signals end up out of sync. To compensate, you can simply slow down the scan signal until your path delay becomes insignificant with respect to the scan-signal period.

A more attractive alternative would be to control and compensate for the path delay without reducing scan-signal speed. Pursuing this approach, Acculogic has just patented a test-data edge-control technology that carries trigger and response signals between tester and DUT over data-grade wire. The technology correlates scan-chain data to within 10-ns resolution regardless of total path delay.

Acculogic’s approach aims to optimize the speed of each scan chain. Another approach to speeding boundary-scan test and programming functions is to add additional TAPs, one to establish a scan chain for boundary-scan tests of standard logic devices and perhaps one for each high-capacity programmable device on the board. But additional TAPs place substantial burdens on your edge connectors or board-surface real estate. In addition, you’ll have to decide how many TAPs to provide at the design stage. If you get into production with a single-TAP PCB and find that throughput is inadequate, you’ll have no recourse.

Far from cowering in the face of the competitive threat from boundary-scan’s virtual nails, ATE vendors have long recognized that their real beds of nails will always provide a larger window into a board’s workings than will a few TAPs at an edge connector. In-circuit tester makers like Agilent Technologies, GenRad, and Teradyne have co-opted the boundary-scan threat by developing software that lets their testers control TAPs via accessible copper nodes on a board’s surface, thus freeing up edge-connector pins from TAP overhead.

With a boundary-scan-capable in-circuit tester, you can use the virtual nails of the scan chain to probe buried and otherwise hidden nodes of scan-compatible devices, as long as you provide bed-of-nails access to the associated TAPs. Keep in mind that few PCBs are populated solely by scan-compatible devices; you can use a bed-of-nails to exercise onboard non-scan components. You may be using an ASIC designed before boundary-scan-synthesis tools became widely available, you may find it cost-effective to use an off-the-shelf part that’s not scan compatible, or your board might contain a significant number of analog parts. There are scan-like techniques for testing analog parts; the DAC example above alludes to one. And the IEEE has recently approved an analog boundary-scan standard. (We will cover the standard—1149.4²—and associated analog scan techniques in an upcoming issue.) For now, though, a bed-of-nails in-circuit tester remains a flexible choice for testing PCBs containing mixes of scan and non-scan parts ( Fig. 2).

Figure 2. In this circuit combining a non-scan-compatible inverter with two scan-compatible parts, the inverter output can wreak havoc with scan-chain data. A bed-of-nails tester can force the non-scan component into a high-impedance output state, enabling boundary-scan test data to flow unimpeded.

Consider Software Development

Of course, an ATE system rarely constitutes an optimum development platform. It’s seldom available to developers, and it’s not convenient when it is available. Boundary-scan controllers, however, are ideal for the lab. Many plug right in to your PC, so they don’t clutter up your bench. For the ultimate in portability, you can select a PC Card version for your laptop. If a single PC’s controllers turn out to be inadequate for your production-test needs, you can buy a dedicated boundary-scan-controller card cage from firms like Goepel to upgrade your capacity.

You could also choose to move your production test to an ATE platform, although this approach raises compatibility issues, and it generally requires that you deal with a different software environment. If you want to use a controller card in the lab but anticipate the need for in-circuit testing in production, you might benefit from synergistic relationships among controller and ATE vendors that have resulted in a similar software environment across controllers and ATE platforms. Acculogic, for example, supports Teradyne’s Victory boundary-scan software, and Corelis supports Agilent Technologies’ boundary-scan software for the HP 3070 in-circuit tester.

Such an approach won’t guarantee a smooth transition—you’ll still need test-point or edge-connector access to the TAPs for your development efforts, and you’ll have to make sure nodes associated with the TAPs that are accessible through test points in the lab aren’t buried beyond the reach of a bed of nails during the board-layout process. Nevertheless, a common software environment can help ensure that your test program will function in production the way you intended as long as you can connect in-circuit test signals to appropriate nodes.

Take to the Air

The edge connector (or dedicated TAP connector) and the bed of nails represent two ways of getting boundary-scan test data through the scan chain. A third option is the flying prober—it’s attractive for small production runs that don’t justify the cost of developing a custom bed-of-nails fixture. Teradyne’s Victory software and Javelin 1004 flying prober are one hardware/software combination that provide boundary-scan capabilities in this format. Although Acculogic does not make a flying prober, it is adapting its FlashRiter high-speed boundary-scan device-programmer technology for use with third-party flying probers such as Teradyne’s. Of course, as for in-circuit test, you’ll need to ensure all your TAP signals are accessible to the flying prober.

You’re likely to find yourself using various combinations of controllers and ATE systems as you bring your designs into production. And don’t ignore field service—TAP access can be a valuable tool for evaluating products that fail in the field. Since throughput is less of an issue in field service, you might consider providing several parallel scan chains to speed production test while making an additional chain available that provides critical data for field-service representatives evaluating conformally coated boards. The emerging boundary-scan platforms are offering increasing flexibility throughout a product’s life cycle. T&MW

FOOTNOTES

1. Wible, Kevin, “CPLD Background,” Test & Measurement World, January 1999, p. 50.  

2. IEEE 1149.4, Mixed-Signal Test Bus, IEEE, Piscataway, NJ, 800-678-4333, grouper.ieee.org/groups/1149/4/

FOR FURTHER READING

“10 Hot Issues When Considering Buying Your Boundary-Scan Toolset,” Asset-Intertech Inc., Richardson, TX, 1999, support.asset-intertech.com/10hot.htm.

Albee, Alan, “Boundary-Scan and In-Circuit Test Combined: Strategy and Benefits,” Nepcon West 1999 Proceedings.

 You can contact Rick Nelson at rnelson@tmworld.com .